SI4031-B1-FM Silicon Laboratories Inc, SI4031-B1-FM Datasheet - Page 5

• Manufacturer Part Number: SI4031-B1-FM
• Description: IC TX 240-930MHZ -8-13DB 20VQFN
• Manufacturer: Silicon Laboratories Inc
• Type: ISM Transmitterr

Specifications of SI4031-B1-FM

• Package / Case: 20-VQFN
• Frequency: 240MHz ~ 930MHz
• Applications: General Purpose
• Modulation Or Protocol: FSK, GFSK, OOK
• Data Rate - Maximum: 256 kbps
• Power - Output: 13dBm
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 240 MHz to 930 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 30 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si4030/31/32-B1
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I S T OF
IGURES
Figure 1. SPI Timing.................................................................................................................. 15
Figure 2. SPI Timing—READ Mode ..........................................................................................16
Figure 3. SPI Timing—Burst Write Mode .................................................................................. 16
Figure 4. SPI Timing—Burst Read Mode .................................................................................. 16
Figure 5. State Machine Diagram.............................................................................................. 17
Figure 6. TX Timing................................................................................................................... 21
Figure 7. Frequency Deviation .................................................................................................. 25
Figure 8. FSK vs. GFSK Spectrums..........................................................................................27
Figure 9. Microcontroller Connections....................................................................................... 30
Figure 10. PLL Synthesizer Block Diagram............................................................................... 31
Figure 11. FIFO Threshold ........................................................................................................34
Figure 12. Packet Structure....................................................................................................... 35
Figure 13. Multiple Packets in TX Packet Handler .................................................................... 36
Figure 14. Operation of Data Whitening, Manchester Encoding, and CRC .............................. 37
Figure 15. Manchester Coding Example ...................................................................................37
Figure 16. POR Glitch Parameters............................................................................................ 39
Figure 17. General Purpose ADC Architecture ......................................................................... 41
Figure 18. Temperature Ranges using ADC8 ........................................................................... 43
Figure 19. WUT Interrupt and WUT Operation.......................................................................... 46
Figure 20. Si4031 Reference Design Schematic ...................................................................... 48
Figure 21. 20-Pin Quad Flat No-Lead (QFN) ............................................................................54
Figure 22. PCB Land Pattern .................................................................................................... 55
Rev 1.1
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