SI4031-B1-FM Silicon Laboratories Inc, SI4031-B1-FM Datasheet - Page 20

• Manufacturer Part Number: SI4031-B1-FM
• Description: IC TX 240-930MHZ -8-13DB 20VQFN
• Manufacturer: Silicon Laboratories Inc
• Type: ISM Transmitterr

Specifications of SI4031-B1-FM

• Package / Case: 20-VQFN
• Frequency: 240MHz ~ 930MHz
• Applications: General Purpose
• Modulation Or Protocol: FSK, GFSK, OOK
• Data Rate - Maximum: 256 kbps
• Power - Output: 13dBm
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 240 MHz to 930 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 30 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si4030/31/32-B1
3.3. Interrupts
The Si4030/31/32 is capable of generating an interrupt signal when certain events occur. The chip notifies the
microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal
will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown
below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers
03h–04h) containing the active Interrupt Status bit. The nIRQ output signal will then be reset until the next change
in status is detected. The interrupts must be enabled by the corresponding enable bit in the Interrupt Enable
Registers (Registers 05h–06h). All enabled interrupt bits will be cleared when the microcontroller reads the
interrupt status register. If the interrupt is not enabled when the event occurs it will not trigger the nIRQ pin, but the
status may still be read at anytime in the Interrupt Status registers.
Add R/W Function/Descript
See “AN466: Si4030/31/32 Register Descriptions” for a complete list of interrupts.
20
03
04
05 R/W
06 R/W
R
R
Interrupt Enable 1
Interrupt Enable 2
Interrupt Status 1
Interrupt Status 2
ion
Reserved Reserved Reserved Reserved iwut
Reserved Reserved Reserved Reserved enwut
enfferr
ifferr
D7
entxffafull entxffaem Reserved enext enpksent Reserved Reserved
itxffafull
D6
itxffaem
D5
Rev 1.1
Reserved iext
D4
D3
ipksent Reserved Reserved
enlbd
ilbd
D2
enchiprdy
ichiprdy
D1
enpor
ipor
D0
POR Def.
00h
01h
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