SI4031-B1-FM Silicon Laboratories Inc, SI4031-B1-FM Datasheet - Page 15

• Manufacturer Part Number: SI4031-B1-FM
• Description: IC TX 240-930MHZ -8-13DB 20VQFN
• Manufacturer: Silicon Laboratories Inc
• Type: ISM Transmitterr

Specifications of SI4031-B1-FM

• Package / Case: 20-VQFN
• Frequency: 240MHz ~ 930MHz
• Applications: General Purpose
• Modulation Or Protocol: FSK, GFSK, OOK
• Data Rate - Maximum: 256 kbps
• Power - Output: 13dBm
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 240 MHz to 930 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 30 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3. Controller Interface
3.1. Serial Peripheral Interface (SPI)
The Si4030/31/32 communicates with the host MCU over a standard 3-wire SPI interface: SCLK, SDI, and nSEL.
The host MCU can read data from the device on the SDO output pin. A SPI transaction is a 16-bit sequence which
consists of a Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data field (DATA)
as demonstrated in Figure 1. The 7-bit address field is used to select one of the 128, 8-bit control registers. The
R/W select bit determines whether the SPI transaction is a read or write transaction. If R/W = 1 it signifies a WRITE
transaction, while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are latched into the
Si4030/31/32 every eight clock cycles. The timing parameters for the SPI interface are shown in Table 9. The
SCLK rate is flexible with a maximum rate of 10 MHz.
To read back data from the Si4030/31/32, the R/W bit must be set to 0 followed by the 7-bit address of the register
from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored n the SDI pin when R/W = 0. The
next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data
read from the selected register will be available on the SDO output pin. The READ function is shown in Figure 2.
After the READ function is completed the SDO pin will remain at either a logic 1 or logic 0 state depending on the
last data bit clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup.
Symbol
t
t
t
t
t
t
t
t
t
t
SW
CH
DS
DH
DD
EN
DE
SH
CL
SS
SCLK
nSEL
Output data delay time
Output disable time
Output enable time
Select high period
Select setup time
SDI
Select hold time
Data setup time
Clock high time
Clock low time
Data hold time
Parameter
MSB
RW
A6 A5
Table 9. Serial Interface Timing Parameters
Min (nsec)
A4
Address
50
80
40
40
20
20
20
20
50
20
A3
Figure 1. SPI Timing
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SDI
Rev 1.1
SCLK
SDO
nSEL
t
t
EN
SS
Data
t
CL
t
CH
Si4030/31/32-B1
Diagram
t
DS
t
DH
LSB
t
DD
xx xx
t
SH
RW A7
t
DE
t
SW
15