SI4031-B1-FM Silicon Laboratories Inc, SI4031-B1-FM Datasheet - Page 31

• Manufacturer Part Number: SI4031-B1-FM
• Description: IC TX 240-930MHZ -8-13DB 20VQFN
• Manufacturer: Silicon Laboratories Inc
• Type: ISM Transmitterr

Specifications of SI4031-B1-FM

• Package / Case: 20-VQFN
• Frequency: 240MHz ~ 930MHz
• Applications: General Purpose
• Modulation Or Protocol: FSK, GFSK, OOK
• Data Rate - Maximum: 256 kbps
• Power - Output: 13dBm
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 240 MHz to 930 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V to 3.6 V
• Supply Current: 30 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5. Internal Functional Blocks
This section provides an overview some of the key blocks of the internal radio architecture.
5.1. Synthesizer
An integrated Sigma Delta (ΣΔ) Fractional-N PLL synthesizer capable of operating from 240–960 MHz is provided
on-chip. The Si4031/32 and Si4030 cover different frequencies. This section discusses the frequency range
covered by all EZRadioPRO devices. Using a ΣΔ synthesizer has many advantages; it provides flexibility in
choosing data rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly
to the loop in the digital domain through the fractional divider which results in very precise accuracy and control
over the transmit deviation.
Depending on the part, the PLL and - modulator scheme is designed to support any desired frequency and
channel spacing in the range from 240–960 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz
(High band). The transmit data rate can be programmed between 0.123–256 kbps, and the frequency deviation
can be programmed between ±1–320 kHz. These parameters may be adjusted via registers as shown in "3.5.
Frequency Control" on page 22.
The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-chip
inductors. The output of the VCO is followed by a configurable divider which will divide down the signal to the
desired output frequency band. The modulus of this divider stage is controlled dynamically by the output from the
- modulator. The tuning resolution is sufficient to tune to the commanded frequency with a maximum accuracy of
312.5 Hz anywhere in the range between 240–960 MHz.
5.1.1. VCO
The output of the VCO is automatically divided down to the correct output frequency depending on the hbsel and
fb[4:0] fields in "Register 75h. Frequency Band Select." The VCO integrates the resonator inductor, tuning varactor,
so no external VCO components are required.
The VCO uses a capacitance bank to cover the wide frequency range specified. The capacitance bank will
automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications this might not
be desirable so the VCO calibration may be skipped by setting the appropriate register.
5.2. Power Amplifier
The Si4032 contains an internal integrated power amplifier (PA) capable of transmitting at output levels between –1
and +20 dBm. The Si4030/31 contains a PA which is capable of transmitting output levels between –8 to +13 dBm.
The PA design is single-ended and is implemented as a two stage class CE amplifier with a high efficiency when
transmitting at maximum power. The PA efficiency can only be optimized at one power level. Changing the output
power by adjusting txpow[2:0] will scale both the output power and current but the efficiency will not be constant.
The PA output is ramped up and down to prevent unwanted spectral splatter.
Fref = 10 M
PFD
Figure 10. PLL Synthesizer Block Diagram
CP
Modulation
TX
LPF
Sigma
Rev 1.1
Delta-
N
VCO
Selectable
Divider
Si4030/31/32-B1
TX
31