AD6654/PCB Analog Devices Inc, AD6654/PCB Datasheet - Page 80

• Manufacturer Part Number: AD6654/PCB
• Description: BOARD EVALUATION FOR AD6654
• Manufacturer: Analog Devices Inc

Specifications of AD6654/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6554
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6654
Table 37. DRCF Multiply Accumulate Scale Bits
DRCF Scale <1:0>
00
01
10
11
<7:4>: DRCF Decimation Rate. This 4-bit word should be
written with one less than the decimation rate of the DRCF
filter. A value of 0 represents a decimation rate of 1 (no rate
change), and the maximum value of 15 represents a decimation
of 16. Filtering can be implemented regardless of the
decimation rate.
<3:0>: DRCF Decimation Phase Bits. This 4-bit word represents
the decimation phase used by the DRCF filter. The valid range
is 0 up to M
DRCF filter. This word is primarily used for synchronization of
multiple channels of the AD6654, when more than one channel
is used for filtering one signal (one carrier).
DRCF Coefficient Offset <7:0>
This register is used to specify which section of the 64-word
coefficient memory is used for a filter. It can be used to select
between multiple filters that are loaded into memory and
referenced by this pointer. This register is shadowed, and the
filter pointer is updated every time a new filter is started. This
allows the coefficient offset to be written even while a filter is
being computed without disturbing operation. The next sample
comes out of the DRCF with the new filter.
DRCF Taps <6:0>
This register is written with one less than the number of taps
that are calculated by the DRCF filter. The filter length is given
by the decimal value of this register plus 1. A value of 0
represents a 1-tap filter, and a value of 0x28 (40 decimal)
represents a 41-tap filter.
DRCF Start Address <5:0>
This register is written with the starting address of the DRCF
coefficient memory to be updated.
DRCF Final Address <5:0>
This register is written with the ending address of the DRCF
coefficient memory to be updated.
DRCF Coefficient Memory <13:0>
DRCF Memory. This memory consists of 64 words, and each
word is 14 bits wide. The data written to this memory space is
expected to be 14-bit, twos complement format. See the
Decimating RAM Coefficient Filter (DRCF) section for the
method to program the coefficients into the coefficient
memory.
DRCF
− 1, where M
Scale Factor
18.06 dB attenuation (left-shift 3 bits)
12.04 dB attenuation (left-shift 2 bits)
6.02 dB attenuation (left-shift 1 bit)
No scaling (0 dB)
DRCF
is the decimation rate of the
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CRCF Control Register <11:0>
<11>: CRCF Bypass Bit. When this bit is set, the DRCF filter is
bypassed and, therefore, its output is the same as its input.
When this bit is cleared, the CRCF has normal operation as
programmed by its control register.
<10>: Symmetry Bit. When this bit is set, it indicates that the
CRCF is implementing a symmetrical filter and only half the
impulse response needs to be written into the CRCF coefficient
RAM. When this bit is cleared, the filter is asymmetrical and
the complete impulse response of the filter should be written
into the coefficient RAM. When this filter is symmetrical, it can
implement up to 128 filter taps.
<9:8>: CRCF Multiply Accumulate Scale Bits. The output of the
CRCF filter is scaled according to the value of these bits.
Table 38 lists the attenuation corresponding to each setting.
Table 38. CRCF Multiply Accumulate Scale Bits
CRCF Scale<1:0>
00
01
10
11
<7:4>: CRCF Decimation Rate. This 4-bit word should be writ-
ten with one less than the decimation rate of the CRCF filter. A
value of 0 represents a decimation rate of 1 (no rate change) and
the maximum value of 15 represents a decimation of 16.
Filtering operation is done regardless of the decimation rate.
<3:0>: CRCF Decimation Phase. This 4-bit word represents the
decimation phase used by the CRCF filter. The valid range is 0
to MCRCF − 1, where MCRCF is the decimation rate of the
CRCF filter. This word is primarily used for synchronization of
multiple channels of the AD6654, when more than one channel
is used for filtering one signal (one carrier).
CRCF Coefficient Offset <5:0>
This register is used to specify which section of the 64-word
coefficient memory is used for a filter. It can be used to select
between multiple filters that are loaded into memory and
referenced by this pointer. This register is shadowed, and the
filter pointer is updated every time a new filter is started. This
allows the coefficient offset to be written even while a filter is
being computed without disturbing operation. The next sample
comes out of the CRCF with the new filter.
CRCF Taps <6:0>
This register is written with one less than the number of taps
that are calculated by the CRCF filter. The filter length is given
by the decimal value of this register plus 1. A value of 0 repre-
sents a 1-tap filter, and a value of 0x28 (40 decimal) represents a
41-tap filter.
Scale Factor
18.06 dB attenuation (left-shift 3 bits)
12.04 dB attenuation (left-shift 2 bits)
6.02 dB attenuation (left-shift 1 bit)
No scaling (0 dB)