AD6654/PCB Analog Devices Inc, AD6654/PCB Datasheet - Page 53

• Manufacturer Part Number: AD6654/PCB
• Description: BOARD EVALUATION FOR AD6654
• Manufacturer: Analog Devices Inc

Specifications of AD6654/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6554
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PARALLEL PORT OUTPUT
The AD6654 incorporates three independent 16-bit parallel
ports for output data transfer. The three parallel output ports
share a common clock, PCLK. Each port consists of a 16-bit
data bus, request signal, acknowledge signal, three channel
indicator pins, one I/Q indicator pin, one gain word indicator
pin, and a common shared PCLK pin. The parallel ports can be
configured to function in master mode or slave mode. By
default, the parallel ports are in slave mode on power-up.
Each parallel port can output data from any or all of the AGCs,
using the 1-bit enable bit for each AGC in the parallel port
control register. Even when the AGC is not required for a
certain channel, the AGC can be bypassed, but the data is still
received from the bypassed AGC. The parallel port
functionality is programmable through the two parallel port
control registers.
Each parallel port can be programmed individually to operate
in either interleaved I/Q mode or parallel I/Q mode. The mode
is selected using a 1-bit data format bit in the parallel port
control register. In both modes, the AGC gain word output can
be enabled using a 1-bit append gain bit in the parallel port
control register for individual output ports. There are six enable
bits per output port, one for each AGC in the corresponding
parallel port.
INTERLEAVED I/Q MODE
Parallel port channel mode is selected by writing a 0 to the data
format bit for the parallel port in consideration. In this mode,
I and Q words from the AGC are output on the same 16-bit data
bus on a time-multiplexed basis. The 16-bit I word is output
followed by the 16-bit Q word. The specific AGCs output by the
port are selected by setting individual bits for each of the AGCs
in the parallel port control register. Figure 57 shows the timing
diagram for the interleaved I/Q mode.
PxCH [2:0]
Px [15:0]
PxGAIN
PxACK
PxREQ
PCLK
PxIQ
Figure 57. Interleaved I/Q Mode Without an AGC Gain Word
t
DPREQ
t
DPIC
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LOGIC LOW ‘0’
PxCH [2:0] = CHANNEL NO.
t
I [15:0]
t
DPP
DPCH
When an output data sample is available for output from an
AGC, the parallel port initiates the transfer by pulling the
PxREQ signal high. In response, the processor receiving the
data needs to pull the PxACK signal high, acknowledging that it
is ready to receive the signal. In Figure 57, PxACK is already
pulled high and, therefore, the 16-bit I data is output on the
data bus on the next PCLK rising edge after PxREQ is driven
logic high. The PxIQ signal also goes high to indicate that I data
is available on the data bus. The next PCLK cycle brings the
Q data onto the data bus. In this cycle, the PxIQ signal is driven
low. When I data and Q data are output, the channel indicator
pins PxCH[2:0] indicate the data source (AGC number).
Figure 57 is the timing diagram for interleaved I/Q mode with
the AGC gain word disabled. Figure 58 is a similar timing
diagram with the AGC gain word. In the PCLK cycle after the Q
data, the AGC gain word is output on the data bus and the
PxGAIN signal is pulled high to indicate that the gain word is
available on the parallel port. Therefore, a minimum of three or
four PCLK cycles are required to output one sample of output
data on the parallel port without or with the AGC gain word,
respectively.
PARALLEL I/Q MODE
In this mode, eight bits of I data and eight bits of Q data are
simultaneously output on the data bus during one PCLK cycle.
The I byte is the most significant byte of the port, while the
Q byte is the least significant byte. The PAIQ and PBIQ output
indicator pins are set high during the PCLK cycle. Note that if
data from multiple AGCs are output consecutively, the PAIQ
and PBIQ output indicator pins remain high until data from all
channels is output. The PACH[2:0] and PBCH[2:0] pins provide
a 3-bit binary value indicating the source (AGC number) of the
data currently being output. Figure 59 is the timing diagram for
parallel I/Q mode.
Q [15:0]
AD6654