AD6654/PCB Analog Devices Inc, AD6654/PCB Datasheet - Page 52

• Manufacturer Part Number: AD6654/PCB
• Description: BOARD EVALUATION FOR AD6654
• Manufacturer: Analog Devices Inc

Specifications of AD6654/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6554
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6654
4 exponent plus 8 mantissa bit floating-point representation
similar to the error threshold. This is taken as the initial gain
value before the AGC loop starts operating.
The products of the gain multiplier are the AGC scaled outputs
with a 19-bit representation. These are, in turn, used as I and Q
for calculating the power, and the AGC error and loop are
filtered to produce the signal gain for the next set of samples.
These AGC scaled outputs can be programmed to have 4-, 5-,
6-, 7-, 8-, 10-, 12-, or 16-bit widths by using the AGC output
word-length word in the AGC control register. The AGC scaled
outputs are truncated to the required bit widths by using the
clipping circuitry, as shown in Figure 56.
Average Samples Setting
Though it is complicated to express the exact effect of the
number of averaging samples by using equations, intuitively it
has a smoothing effect on the way the AGC loop addresses a
sudden increase or a spike in the signal level. If averaging of
four samples is used, the AGC addresses a sudden increase in
signal level more slowly compared to no averaging. The same
applies to the manner in which the AGC addresses a sudden
decrease in the signal level.
DESIRED CLIPPING LEVEL MODE
Each AGC can be configured so that the loop locks onto a
desired clipping level or a desired signal level. Desired clipping
level mode is selected by writing Logic 1 in the AGC clipping
error mode bit in the AGC control register. For signals that tend
to exceed the bounds of the peak-to-average ratio, the desired
clipping level option provides a way to prevent truncating those
signals and still provide an AGC that attacks quickly and settles
to the desired output level. The signal path for this mode of
operation is shown with dotted lines in Figure 56; the operation
is similar to the desired signal level mode.
First, the data from the gain multiplier is truncated to a lower
resolution (4, 5, 6, 7, 8, 10, 12, or 16 bits) as set by the AGC
output word-length word in the AGC control register. An error
term (for both I and Q) is generated that is the difference
between the signals before and after truncation. This term is
passed to the complex squared magnitude block, for averaging
and decimating the update samples and taking their square root
to find rms samples as in desired signal level mode. In place of
the request desired signal level, a desired clipping level is
subtracted, leaving an error term to be processed by the second-
order loop filter.
The rest of the loop operates the same way as the desired signal
level mode. This way, the truncation error is calculated and the
AGC loop operates to maintain a constant truncation error
level. The only register setting that is different from the desired
signal level mode settings is that the desired clipping level is
stored in the AGC desired level registers instead of in the
request signal level.
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AGC SYNCHRONIZATION
When the AGC output is connected to a RAKE receiver, the
RAKE receiver can synchronize the average and update section
to update the average power for AGC error calculation and loop
filtering. This external sync signal synchronizes the AGC
changes to the RAKE receiver and makes sure that the AGC
gain word does not change over a symbol period, which,
therefore, provides a more accurate estimation. This synchroni-
zation is accomplished by setting the appropriate bits of the
AGC control register.
Sync Select Alternatives
The AGC can receive a sync as follows:
•
•
•
When the channel sync select bit of the AGC control register is
Logic 1, the AGC receives the sync signal used by the NCO of
the corresponding channel for the start. When this bit is Logic 0,
the pin sync defined by the 2-bit SYNC pin select word in the
AGC control register provides the sync to the AGC. Apart from
these two methods, the AGC control register also has a sync
now bit that can be used to provide a sync to the AGC by
writing to this register through the microport or serial port.
SYNC PROCESS
Regardless of how a sync signal is received, the syncing process
is the same. When a sync is received, a start hold-off counter is
loaded with the 16-bit value in the AGC hold-off register, which
initiates the countdown. The countdown is based on the ADC
input clock. When the count reaches 1, a sync is initiated. When
a sync is initiated, the CIC decimation filter dumps the current
value to the square root, error estimation, and loop filter blocks.
After dumping the current value, it starts working toward the
next update value. Additionally on a sync, AGC can be initial-
ized, if the initialize AGC on sync bit is set in the AGC control
register. During initialization, the CIC accumulator is cleared
and new values for CIC decimation, number of averaging
samples, CIC scale, signal gain, open-loop Gain K
and the Pole P parameter are loaded from their respective
registers. When the initialize on sync bit is cleared, these
parameters are not loaded from the registers.
This sync process is also initiated when a channel comes out of
sleep by using the start sync to the NCO. An additional feature
is the first sync only bit in the AGC control register. When this
bit is set, only the first sync initiates the process and the remain-
ing sync signals are ignored. This is useful when syncing using a
pin sync. A sync is required only on the first pulse on this pin.
These additional features make AGC synchronization more
flexible and applicable to varied circumstances
Channel sync: The sync signal is used to synchronize the
NCO of the channel under consideration.
Pin sync: Selects one of the four SYNC pins.
Sync now bit: Through the AGC control register.
1
and Gain K
2
,