AD6654/PCB Analog Devices Inc, AD6654/PCB Datasheet - Page 3

• Manufacturer Part Number: AD6654/PCB
• Description: BOARD EVALUATION FOR AD6654
• Manufacturer: Analog Devices Inc

Specifications of AD6654/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6554
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Channel RAM Coefficient Filter (CRCF) ....................................45
Interpolating Half-Band Filter.......................................................47
Output Data Router ........................................................................48
Automatic Gain Control.................................................................49
Parallel Port Output ........................................................................53
User-Configurable Built-In Self-Test (BIST)...............................57
Chip Synchronization .....................................................................58
Decimation Phase .......................................................................43
Maximum Number of Taps Calculated....................................43
Programming DRCF Registers for
an Asymmetrical Filter ...............................................................44
Programming DRCF Registers for a Symmetric Filter ..........44
Bypass ...........................................................................................45
Scaling...........................................................................................45
Symmetry .....................................................................................45
Coefficient Offset ........................................................................45
Decimation Phase .......................................................................45
Maximum Number of TAPS Calculated..................................45
Programming CRCF Registers for an
Asymmetrical Filter ....................................................................46
Programming CRCF Registers for a Symmetrical Filter .......46
Interleaving Data.........................................................................48
AGC Loop ....................................................................................49
Desired Signal Level Mode ........................................................50
Desired Clipping Level Mode....................................................52
AGC Synchronization.................................................................52
SYNC Process ..............................................................................52
Interleaved I/Q Mode .................................................................53
Parallel IQ Mode .........................................................................53
Master/Slave PCLK Modes ........................................................55
Parallel Port Pin Functions ........................................................56
Start ...............................................................................................58
Rev. 0 | Page 3 of 88
Serial Port Control ..........................................................................60
Microport .........................................................................................70
Memory Map ...................................................................................72
DDC Design Notes .........................................................................85
Outline Dimensions........................................................................87
REVISION HISTORY
4/05—Revision 0: Initial Version
HOP ..............................................................................................58
Hardware Interface .....................................................................60
SPI Mode Timing........................................................................62
SPORT Mode Timing.................................................................64
Programming Indirect Addressed Registers
Using Serial Port..........................................................................67
Connecting the AD6654 Serial Port to a Blackfin DSP .........69
Intel (Inm) Mode ........................................................................70
Motorola (MNM) Mode ............................................................70
Accessing Multiple AD6654 Devices .......................................71
Reading the Memory Map Table...............................................72
Bit Format ....................................................................................72
Open Locations ...........................................................................72
Default Values..............................................................................72
Logic Levels..................................................................................72
Global Register Map ...................................................................74
Input Port Register Map.............................................................76
Channel Register Map ................................................................78
MRCF Coefficient Memory.......................................................79
Output Port Register Map..........................................................82
Ordering Guide ...........................................................................87
AD6654