AD6654/PCB Analog Devices Inc, AD6654/PCB Datasheet - Page 20

• Manufacturer Part Number: AD6654/PCB
• Description: BOARD EVALUATION FOR AD6654
• Manufacturer: Analog Devices Inc

Specifications of AD6654/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6554
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6654
Name
DDC INPUTS
CLK
SYNC0
SYNC1
SYNC2
SYNC3
DDC OUTPUTS
EXPC [2:0]
DDC OUTPUT PORTS
PCLK
PADATA[15:0]
PACH[2:0]
PAIQ
PAGAIN
PAACK
PAREQ
PBDATA[15:0]
PBCH[2:0]
PBIQ
PBGAIN
PBACK
PBREQ
PCDATA[15:0]
PCCH[2:0]
PCIQ
PCGAIN
PCACK
PCREQ
MICROPORT CONTROL
D[15:0]
A[7:0]
DS (RD)
DTACK (RDY)
R/W (WR)
MODE
CS
CPUCLK
CHIPID[3:0]
SERIAL PORT CONTROL
SCLK
SDO
SDI
STFS
SRFS
SCS
MSB_FIRST
SMODE
MISC PINS
DNC
IRP
RESET
EXT_FILTER
1
2
Pins with internal pull-up resistor of nominal 70 kΩ.
Pins with internal pull-down resistor of nominal 70 kΩ.
1
2
1
1
Type
Input
Input
Input
Input
Input
Output
Bi-dir
Output
Output
Output
Output
Input
Output
Output
Output
Output
Output
Input
Output
Output
Output
Output
Output
Input
Output
Bi-Dir
Input
Input
Output
Input
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Input
Input
-------
Output
Input
Input
Pin Number
A11
T10
R11
P11
T11
D11, C11, B11
T4
See
D8, R5, C8
A8
A9
B8
N6
See
P10, P8, R8
T7
R10
P9
N8
See
M5, A6, R1
P1
R2
E5
P2
See
See
B4
C3
C4
C2
D3
A4
C1, E1, B3, B2
A4
C3
K3
C4
B4
D3
D2
F1
B12, T9
E2
F4
D1
Table 12
Table 12
Table 12
Table 12
Table 12
Function
DDC Clock Input.
Synchronization Input 0. SYNC pins are independent of channels.
Synchronization Input 1.
Synchronization Input 2.
Synchronization Input 3.
External VGA Gain Control Bits. GND all pins if not used.
Parallel Output Port A Data Bus.
Channel Indicator Output Port A.
Parallel Port A I/Q Data Indicator. Logic 1 indicates I data on data bus.
Parallel Port A Gain Word Output Indicator. Logic 1 indicates gain word on data bus.
Parallel Port A Acknowledge (Active High).
Parallel Port A Request (Active High).
Parallel Output Port B Data Bus.
Channel Indicator Output Port B.
Parallel Port B I/Q Data Indicator. Logic 1 indicates I data on data bus.
Parallel Port B Gain Word Output Indicator. Logic 1 indicates gain word on data bus.
Parallel Port B Acknowledge (Active High).
Parallel Port B Request (Active High)
Parallel Output Port C Data Bus.
Channel Indicator Output Port C.
Parallel Port C I/Q Data Indicator. Logic 1 indicates I data on data bus.
Parallel Port C Gain word Output Indicator. Logic 1 indicates gain word on data bus.
Parallel Port C Acknowledge (Active High).
Parallel Port C Request (Active High).
Bidirectional Microport Data. This bus is three-stated when CS is high.
Microport Address Bus.
Active Low Data Strobe, MODE = 1. Active low read strobe when MODE = 0.
Active Low Data Acknowledge, MODE = 1. Microport status pin when MODE = 0. Terminate
to VDDIO through external 1 kΩ pull-up resistor.
Read/Write Strobe, MODE = 1. Active low write strobe when MODE = 0.
Mode Select. Logic 0 = Intel® mode, Logic 1 = Motorola mode.
Active Low Chip Select. Logic 1 three-states the microport data bus.
Microport CLK Input. (Input only.)
Chip ID Input Pins.
Serial Clock. Should have a rise/fall time of 3ns max.
Serial Port Data Output. Terminate to VDDIO through external 1 kΩ pull-up resistor.
Serial Port Data Input.
Serial Transmit Frame Sync.
Serial Receive Frame Sync.
Serial Chip Select.
Most Significant Bit_First. Selects MSB_FIRST into SDI pin, and MSB_FIRST out of SDO pin.
Logic 1 = MSB_FIRST; Logic 0 = LSB_FIRST
Serial Mode Select.
Do Not Connect.
Interrupt Pin (Active Low). Terminate to VDDIO through external 1 kΩ pull-up resistor.
Master Reset, Active Low.
PLL Loop Filter (Analog Pin). Connect to VDDCORE through series 250 Ω and 0.01 µF
capacitor.
Parallel Output Port Clock. PCLK is bi-directional: master mode = output, slave mode = input.
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