AD6654/PCB Analog Devices Inc, AD6654/PCB Datasheet - Page 51

• Manufacturer Part Number: AD6654/PCB
• Description: BOARD EVALUATION FOR AD6654
• Manufacturer: Analog Devices Inc

Specifications of AD6654/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6554
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Therefore, in the previous example, if the desired signal level is
−13.8 dB, the request level R is programmed to be −16.54 dB,
compensating for the offset.
This request signal level is programmed in the 8-bit AGC
desired level register. This register has a floating-point
representation, where the 2 MSBs are exponent bits and the
6 LSBs are mantissa bits. The exponent is in steps of 6.02 dB,
and the mantissa is in steps of 0.094 dB. For example, a value
10’100101 represents 2 × 6.02 + 37 × 0.094 = 15.518 dB.
The AGC provides a programmable second-order loop filter.
The programmable parameters Gain 1 (K
Threshold E, and Pole P completely define the loop filter
characteristics. The error term after subtracting the request
signal level is processed by the loop filter, G(z). The open loop
poles of the second-order loop filter are 1 and P, respectively.
The loop filter parameters, Pole P and Gain K, allow the
adjustment of the filter time constant that determines the
window for calculating the peak-to-average ratio.
Depending on the value of the error term that is obtained after
subtracting the request signal level from the actual signal level,
either Gain Value K
than the programmable threshold E, K
allows a fast loop when the error term is high (large
convergence steps required), and a slower loop function when
the error term is smaller (almost converged).
The open-loop gain used in the second-order loop G(z) is given
by one of the following equations:
The open-loop transfer function for the filter, including the gain
parameter, is
If the AGC is properly configured in terms of offset in the
request level, then there are no gains in the AGC loop except for
K, the filter gain. Under these circumstances, a closed-loop
expression for the AGC loop is given by
Program K
AGC loop Gain 1 and Gain 2, and AGC pole location registers
from 0 to 0.996 in steps of 0.0039 using 8-bit representation. For
example, 1000 1001 represent (137/256 = 0.535156). The error
threshold value is programmable between 0 dB and 96.3 dB in
steps of 0.024 dB. This value is programmed in the 12-bit AGC
K = K
K = K
G
G
CLOSED
(
z
)
1
2
1
, if Error < Error Threshold
, if Error > Error Threshold
=
and K
1
(
−
z
)
(
1
=
2
(the gain parameters) and Pole P through
1
+
1
or Gain Value K
P
+
G
Kz
)
(
G
z
z
(
−
)
−
z
1
1
)
+
=
1
Pz
+
−
(
2
K
2
−
is used. If the error is less
1
or K
1
1
−
Kz
), Gain 2 (K
P
2
−
)
is used. This
z
1
−
1
+
Pz
2
), Error
−
2
Rev. 0 | Page 51 of 88
error threshold register, using floating-point representation. It
consists of four exponent bits and eight mantissa bits. Exponent bits
are in steps of 6.02 dB and mantissa bits are in steps of 0.024 dB.
For example, 0111’10001001 represents 7 × 6.02 + 137 × 0.024 =
45.428 dB.
The user defines the open-loop Pole P and Gain K, which also
directly impact the placement of the closed-loop poles and filter
characteristics. These closed-loop poles, P
of the denominator of the previous closed-loop transfer
function and are given by
Typically, the AGC loop performance is defined in terms of its
time constant or settling time. In this case, the closed-loop poles
should be set to meet the time constants required by the AGC
loop.
The relationship between the time constant and the closed-loop
poles that can be used for this purpose is
where τ
Pole P
The time constants can also be derived from settling times as
given by
M
time or time constant are chosen by the user. The sample rate is
the sample rate of the stream coming into the AGC. If channels
were interleaved in the output data router, then the combined
sample rate into the AGC should be considered. This rate
should be used in the calculation of poles in the previous
equation, where the sample rate is mentioned.
The loop filter output corresponds to the signal gain that is
updated by the AGC. Because all computation in the loop filter
is done in logarithmic domain (to the Base 2) of the samples,
the signal gain is generated using the exponent (power of 2) of
the loop filter output.
The gain multiplier gives the product of the signal gain with
both the I and Q data entering the AGC section. This signal
gain is applied as a coarse 4-bit scaling and then as a fine scale
8-bit multiplier. Therefore, the applied signal gain is from 0 to
96.3 dB in steps of 0.024 dB. The initial signal gain is program-
mable using the AGC signal gain register. This register is again a
CIC
P
P
τ
(CIC decimation is from 1 to 4,096), and either the settling
2
1
1,2
=
.
,
1, 2
P
2
=
%
2
are the time constants corresponding to Pole P
exp
=
settling
(
1
⎡
⎢
⎢
⎣
4
+
Sample
P
time
−
K
M
or
)
Rate
CIC
±
5
%
(
×
1
settling
2
τ
+
1,
P
3
2
−
⎤
⎥
⎥
⎦
K
time
1
)
2
and P
−
4
P
2
, are the roots
AD6654
1
and