AD6654/PCB Analog Devices Inc, AD6654/PCB Datasheet - Page 56

• Manufacturer Part Number: AD6654/PCB
• Description: BOARD EVALUATION FOR AD6654
• Manufacturer: Analog Devices Inc

Specifications of AD6654/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6554
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6654
PARALLEL PORT PIN FUNCTIONS
Table 25 describes the functions of the pins used by the parallel ports.
Table 25. Parallel Port Pin Functions
Pin Name
PCLK
PAREQ, PBREQ,
PCREQ
PAACK, PBACK,
PCACK
PAIQ, PBIQ, PCIQ
PAGAIN, PBGAIN,
PCGAIN
PACH[2:0], PBCH[2:0],
PCCH[2:0]
PADATA[15:0],
PBDATA[15:0],
PCDATA[15:0]
I/O
I/O
O
I
Function
Parallel Clock. PCLK can operate as a master or as a slave. This setting is dependent on the 1-bit PCLK master
mode bit in the Parallel Port Control 2 register. As an output (master mode), the maximum frequency is
CLK/N, where CLK is the AD6654 clock and N is an integer divisor of 1, 2, 4, or 8. As an input (slave mode), it
can be asynchronous or synchronous relative to the AD6654 CLK. This pin powers up as an input to avoid
possible contentions. Parallel port output pins change on the rising edge of PCLK.
Active High Output. Synchronous to PCLK. A logic high on this pin indicates that data is available to be
shifted out of the port. When an acknowledge signal is received, data starts shifting out and this pin remains
high until all pending data has been shifted out.
Active High Asynchronous Input. Applying a logic low on this pin inhibits parallel port data shifting. Applying
a logic high to this pin when REQ is high causes the parallel port to shift out data according to the
programmed data mode. ACK is sampled on the rising edge of PCLK. Assuming that REQ is asserted, the
latency from the assertion of ACK to data appearing at the parallel port output is no more than 1.5 PCLK
cycles. ACK can be continuously held high; in this case, when data becomes available, shifting begins 1 PCLK
cycle after the assertion of REQ (see Figure 57, Figure 58, Figure 59, and Figure 60).
Parallel Output Gain Data Indicators High whenever I data is present on the parallel port data bus; otherwise
low. In parallel I/Q mode, both I data and Q data are available at the same time and, therefore, the PxIQ signal
is pulled high.
Parallel Output Gain Word Indicators. High whenever the AGC gain word is present on the parallel port data
bus; otherwise low.
Channel Indicator Output Ports. These pins identify data in both of the parallel port modes. The 3-bit value
identifies the source of the data (AGC number) on the parallel port when it is being shifted out.
Parallel Output Port Data Bus. Output format is twos complement. In parallel I/Q mode, 8-bit data is present;
in interleaved I/Q mode, 16-bit data is available.
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