AD6654/PCB Analog Devices Inc, AD6654/PCB Datasheet - Page 28

• Manufacturer Part Number: AD6654/PCB
• Description: BOARD EVALUATION FOR AD6654
• Manufacturer: Analog Devices Inc

Specifications of AD6654/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6554
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6654
APPLICATION INFORMATION
ADC CONFIGURATION NOTES
Encoding the AD6654 ADC
The AD6654 encode signal must be a high quality, extremely
low phase noise source to prevent degradation of performance.
Maintaining 14-bit accuracy places a premium on encode clock
phase noise. SNR performance can easily degrade by 3 dB to
4 dB with 70 MHz analog input signals when using a high jitter
clock source. See the AN-501, Aperture Uncertainty and ADC
System Performance Application Note , for details.
For optimum performance, the AD6654 ADC front end must
be clocked differentially. The encode signals are usually ac-
coupled into the ENC+ and ENC− pins via a transformer or
capacitors. The ENCODE pins are biased internally and require
no additional bias.
Figure 37 shows one preferred method for clocking the
AD6654. The clock source (low jitter) is converted from single-
ended to differential using an RF transformer. The back-to-back
Schottky diodes across the secondary of the transformer limit
clock excursions into the AD6654 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD6654,
and limits the noise presented to the encode inputs.
If a low jitter clock is available, another option is to ac-couple a
differential ECL/PECL signal to the encode input pins as shown
in Figure 38. A device that offers excellent jitter performance is
the MC100EL16 (or same family) from ON Semiconductor®.
Driving the Analog Inputs
As with most high speed, high dynamic range ADCs, the analog
input to the AD6654 front end is differential. Differential inputs
improve on-chip performance, because signals are processed
through attenuation and gain stages. Most of the improvement
is a result of differential analog stages having high rejection of
even-order harmonics.
SOURCE
CLOCK
Figure 37. Crystal Clock Oscillator-Differential Encode
PECL
ECL/
Figure 38. Differential ECL for Encode
0.1µF
T1-4T
VT
VT
HSMS2812
0.1µF
0.1µF
DIODES
ENC–
ENC+
AD6654
ENC+
ENC–
AD6654
Rev. 0 | Page 28 of 88
There are also benefits at the PCB level. First, differential inputs
have high common-mode rejection to stray signals such as
ground and power noise. Second, they provide good rejection to
common-mode signals such as local oscillator feed-through.
The AD6654 analog input pins, AIN+ and AIN−, are centered
at 2.4 V, and the signal at each input should swing ±0.55 V
around this voltage. Because AIN+ and AIN− are 180° out of
phase, the full-scale differential analog input signal is 2.2 V p-p.
Each analog input connects through a 500 Ω resistor to the
2.4 V bias voltage and to the input of a differential buffer, as
shown in Figure 36. The resistor network on the input properly
biases the followers for maximum linearity and range.
Therefore, the analog source driving the AD6654 should be
ac-coupled to the input pins. Because the differential input
impedance of the AD6654 is 1 kΩ, the analog input power
requirement is only −2 dBm, simplifying the driver amplifier in
many cases. To take full advantage of this high input
impedance, a 20:1 transformer is required. This is a large ratio
that could result in unsatisfactory performance. In this case, a
lower step-up ratio could be used. The recommended method
for driving the analog input of the AD6654 is to use a 4:1
impedance ratio RF transformer.
For example, if R
with a 4:1 impedance ratio transformer, the input matches to a
50 Ω source with a full-scale drive of 4.8 dBm. Series resistors
(R
isolate the transformer from A/D. This limits the amount of
dynamic current from the A/D flowing back into the secondary
of the transformer. The 50 Ω impedance matching can also be
incorporated on the secondary side of the transformer, as
shown in the evaluation board schematic.
In applications where dc-coupling, or additional gain is
required, use a differential output op amp from Analog Devices,
Inc., such as AD8351, to drive the AD6654 (Figure 40). The
AD8351
provide single-ended-to-differential conversion.
S
) on the secondary side of the transformer should be used to
ANALOG INPUT
op amp can be driven differentially, or configured to
Figure 39. Transformer-Coupled Analog Input Circuit
SIGNAL
T
is set to 60.4 Ω and R
R
T
ADT4-1WT
0.1µF
R
R
S
S
S
is set to 25 Ω, along
AIN+
AIN–
AD6654