AD6654/PCB Analog Devices Inc, AD6654/PCB Datasheet

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AD6654/PCB

Manufacturer Part Number
AD6654/PCB
Description
BOARD EVALUATION FOR AD6654
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD6654/PCB

Module/board Type
Evaluation Board
For Use With/related Products
AD6554
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
FEATURES
SNR = 90 dB in 1.25 MHz bandwidth to Nyquist
SNR = 87 dB in 1.25 MHz bandwidth to 200 MHz
Integrated 14-bit, 92.16 MSPS ADC
IF sampling frequencies to 200 MHz
Internal 2.4 V reference, 2.2 V p-p analog input range
Internal differential track-and-hold analog input
Processes 4/6 wideband carriers simultaneously
Fractional clock multiplier to 200 MHz
Programmable decimating FIR filters, interpolating
Three 16-bit configurable parallel output ports
User-configurable built-in self-test (BIST) capability
8-/16-bit microport and SPORT/SPI® serial port control
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
half-band filters and programmable AGC loops
with 96 dB range
(VGA LEVEL CONTROL)
M = DECIMATION
L = INTERPOLATION
ENC+
ENC–
AIN+
AIN–
(ADC OVERRANGE)
V
14-BIT ADC FRONT END
REF
(AVAILABLE IN
6-CHANNEL MODEL ONLY)
OVR
SHA
EXP
INTERNAL
TIMING
V
2.4V
ADC
REF
3
14
MATRIX
INPUT
PEAK/
MSMT
GEN
BITS
VDDCORE, VDDIO, GND
PRN
EXP
RMS
AVDD, DRVDD,
NCO
NCO
NCO
NCO
NCO
NCO
FUNCTIONAL BLOCK DIAGRAM
M = 1–32
M = 1–32
M = 1–32
M = 1–32
M = 1–32
M = 1–32
CIC5
CIC5
CIC5
CIC5
CIC5
CIC5
4-CHANNEL AND 6-CHANNEL DIGITAL DOWN CONVERTER
0, 1, 2, 3
SYNC
M = BYP, 2
M = BYP, 2
M = BYP, 2
M = BYP, 2
M = BYP, 2
M = BYP, 2
FIR1
HB1
FIR1
HB1
FIR1
HB1
FIR1
HB1
FIR1
HB1
FIR1
HB1
Figure 1.
Wideband IF to Baseband Receiver
14-Bit, 92.16 MSPS, 4-/6-Channel
MULTIPLIER
M = BYP, 2
M = BYP, 2
M = BYP, 2
M = BYP, 2
M = BYP, 2
M = BYP, 2
APPLICATIONS
Multicarrier, multimode digital receivers
GSM, EDGE, PHS, UMTS, WCDMA, CDMA2000,
Micro and pico cell systems, software radios
Wireless local loop
Smart antenna systems
In-building wireless telephony
Broadband data applications
Instrumentation and test equipment
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
CLOCK
FIR2
FIR2
FIR2
FIR2
FIR2
FIR2
HB2
HB2
HB2
HB2
HB2
HB2
TD-SCDMA, WiMAX
8-BIT/16-BIT MICROPORT
M = 1–16
M = 1–16
M = 1–16
M = 1–16
M = 1–16
M = 1–16
MRCF
DRCF
MRCF
DRCF
MRCF
DRCF
MRCF
DRCF
MRCF
DRCF
MRCF
DRCF
INTERFACE
©2005 Analog Devices, Inc. All rights reserved.
M = 1–16
M = 1–16
M = 1–16
M = 1–16
M = 1–16
M = 1–16
CRCF
CRCF
CRCF
CRCF
CRCF
CRCF
SPI INTERFACE
L = 1, 2
L = 1, 2
L = 1, 2
L = 1, 2
L = 1, 2
L = 1, 2
LHB
LHB
LHB
LHB
LHB
LHB
SPORT/
www.analog.com
AGC
AD6654
PA
PB
PC

Related parts for AD6654/PCB

AD6654/PCB Summary of contents

Page 1

FEATURES SNR = 1.25 MHz bandwidth to Nyquist SNR = 1.25 MHz bandwidth to 200 MHz Integrated 14-bit, 92.16 MSPS ADC IF sampling frequencies to 200 MHz Internal 2.4 V reference, 2.2 V p-p ...

Page 2

AD6654 TABLE OF CONTENTS General Description ......................................................................... 4 Product Highlights ....................................................................... 5 Specifications..................................................................................... 6 Recommended Operating Conditions ...................................... 6 ADC DC Specifications ............................................................... 6 ADC Digital Specifications ......................................................... 6 ADC Switching Specifications.................................................... 7 ADC AC Specifications ............................................................... 7 Electrical Characteristics............................................................. ...

Page 3

Decimation Phase .......................................................................43 Maximum Number of Taps Calculated....................................43 Programming DRCF Registers for an Asymmetrical Filter ...............................................................44 Programming DRCF Registers for a Symmetric Filter ..........44 Channel RAM Coefficient Filter (CRCF) ....................................45 Bypass ...........................................................................................45 Scaling...........................................................................................45 Symmetry .....................................................................................45 Coefficient Offset ........................................................................45 Decimation Phase ...

Page 4

AD6654 GENERAL DESCRIPTION The AD6654 is a mixed-signal IF-to-baseband receiver consisting of a 14-bit, 92.16 MSPS analog-to-digital converter (ADC) and a 4-/6-channel, multimode digital down-converter (DDC) capable of processing up to six WCDMA (wideband code division multiple access) channels. The ...

Page 5

It can also allow complex filtering operations to be achieved in the programmable filters. The digital AGC provides the user with scaled digital outputs based on the rms level of the signal present at the output of the ...

Page 6

AD6654 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Table 1. Parameter (Conditions) 1 AVDD 2 DRVDD VDDCORE 2 VDDIO T AMBIENT 1 Specified for dc supplies with linear rise-time <250 ms. 2 DRVDD and VDDIO can be operated from the same supply. ADC ...

Page 7

ADC SWITCHING SPECIFICATIONS AVDD = 5.0 V, DRVDD = 3.3 V, VDDCORE = 1.8 V, VDDIO = 3.3 V, maximum rated sample rate, differential input, unless otherwise noted. Table 4. Parameter (Conditions) SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate ...

Page 8

AD6654 ELECTRICAL CHARACTERISTICS AVDD = 5.0 V, DRVDD = 3.3 V, VDDCORE = 1.8 V, VDDIO = 3.3 V, maximum rated sample rate, differential input, unless otherwise noted. Table 6. Parameter (Conditions) LOGIC INPUTS (NOT 5 V TOLERANT) Logic Compatibility ...

Page 9

TIMING CHARACTERISTICS Table Parameter CLK TIMING REQUIREMENTS t CLK Period CLK t CLK Width Low CLKL t CLK Width High CLKH INPUT WIDEBAND DATA TIMING REQUIREMENTS ↑CLK to EXP[2:0] Delay t DEXP PARALLEL OUTPUT PORT TIMING ...

Page 10

AD6654 MICROPORT TIMING CHARACTERISTICS Table Parameter MICROPORT CLOCK TIMING REQUIREMENTS t CPUCLK Period CPUCLK t CPUCLK Low Time CPUCLKL t CPUCLK High Time CPUCLKH INM MODE WRITE TIMING (MODE = 0) to ↑CPUCLK Setup Time t 3 ...

Page 11

SERIAL PORT TIMING CHARACTERISTICS Table Parameter SERIAL PORT CLOCK TIMING REQUIREMENTS t SCLK Period SCLK t SCLK Low Time SCLKL t SCLK High Time SCLKH SPI PORT CONTROL TIMING REQUIREMENTS (MODE = 0) SDI to ↑SCLK ...

Page 12

AD6654 TIMING DIAGRAMS RESET CLK CPUCLK SCLK CLK SYNC [3:0] CLK EXPx [2:0] t RESL Figure 2. Reset Timing Requirements t CLKH t CLKL Figure 3. CLK Switching Characteristics t CPUCLKH t CPUCLKL Figure 4. CPUCLK Switching Characteristics t SCLKH ...

Page 13

PCLK t SPA PxACK t DPREQ PxREQ t DPP Px [15:0] PxIQ PxCH [2:0] PxGAIN Figure 8. Master Mode PxACK to PCLK Switching Characteristics PCLK PxACK t DPREQ PxREQ t DPP Px [15:0] t PxIQ DPIQ PxCH [2:0] PxGAIN Figure ...

Page 14

AD6654 CPUCLK SAM A [7:0] t SAM D [15:0] RDY NOTE: t ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM CPUCLK CYCLES. ACC CPUCLK t SC ...

Page 15

CPUCLK R SAM A [7:0] VALID ADDRESS t SAM D [15:0] VALID DATA DTACK t ACC NOTE: t ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. IT CAN VARY FROM 3 TO ...

Page 16

AD6654 SCLK t SSCS SCS SMODE t SSDI SDI t SSRFS SRFS MODE SCLK t SSCS SCS SMODE SDO t SSTFS STFS MODE SCLK t SSCS SCS SMODE t SSDI SDI D0 MODE LOGIC 1 t HSDI ...

Page 17

SCLK t SSCS SCS SMODE t DSDO SDO D0 D1 MODE Figure 17. SPI Mode Read Timing Characteristics LOGIC LOGIC 0 Rev Page AD6654 t HSCS D7 ...

Page 18

AD6654 ABSOLUTE MAXIMUM RATINGS Table 10. Parameter Rating AVDD 0 to +7.0 V DRVDD 0 to +4.0 V VDDCORE −0 +2.2 V VDDIO 0 to +4.0 V Analog/Encode Input Voltage 0 to AVDD Analog Input Current 25 mA ...

Page 19

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CPUCLK A DGND D14 D12 (SCLK CHIPID3 CHIPID2 (RD, SRFS) R/W DTACK C CHIPID0 MODE (RDY, (WR, SDO) STFS) EXT _ MSB PC6 FILTER FIRST ...

Page 20

AD6654 Name Type Pin Number DDC INPUTS CLK Input A11 SYNC0 Input T10 SYNC1 Input R11 SYNC2 Input P11 SYNC3 Input T11 DDC OUTPUTS EXPC [2:0] Output D11, C11, B11 DDC OUTPUT PORTS PCLK Bi-dir T4 PADATA[15:0] Output Table 12 ...

Page 21

Table 12. Pin Listing for Power, Ground, and Data Buses Name Pin Number AVDD A13, A14, B13, B14, C12, C13, C14, D13, D14, E13, E14, F13, F14, G13, G14, H13, H14, J13, J14, K13, K14, L13, L14, M13, M14, N13, ...

Page 22

AD6654 TYPICAL PERFORMANCE CHARACTERISTICS +85° ENCODE = 92.16MSPS AIN = –1dBFS 110 AIN FREQUENCY (MHz) Figure 19. ADC Noise vs. Analog Frequency (46.08 MHz BW) 120 110 dBFS ...

Page 23

AIN = –1dBFS –15 SNR = 88dB (1.25MHz BW) 32k FFT –30 –45 –60 –75 –90 –105 –120 –135 –150 FREQUENCY (Hz) Figure 25. CDMA Single Tone AIN = 151.5 MHz; ENC = 92.16 MSPS 0 AIN = –1dBFS ...

Page 24

AD6654 0 AIN = –7dBFS –15 32k FFT F1 –30 –45 –60 –75 –90 –105 –120 –135 –150 FREQUENCY (Hz) Figure 31. CDMA Two Tones at 55 MHz and 56 MHz; ENC = 92.16 MSPS 110 100 ...

Page 25

ADC EQUIVALENT CIRCUITS AVDD 2.4V 100µA Figure 33. ADC 2.4 V Reference LOADS AVDD AVDD 10kΩ ENC+ 10kΩ LOADS Figure 34. ADC Encode Inputs AVDD V REF V AVDD AVDD 10kΩ ENC– 10kΩ Rev Page ...

Page 26

AD6654 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Differential Analog Input Resistance, Capacitance, and Impedance The real and complex impedances ...

Page 27

THEORY OF OPERATION ADC ARCHITECTURE The AD6654 analog-to-digital converter (ADC) front end employs a 3-stage subrange architecture. This design approach achieves the required accuracy and speed, while maintaining low power consumption. The AD6654 front end has complementary analog input pins, ...

Page 28

AD6654 APPLICATION INFORMATION ADC CONFIGURATION NOTES Encoding the AD6654 ADC The AD6654 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock phase noise. ...

Page 29

INHI OPHI 25Ω BALANCE R G AD8351 50Ω SOURCE OPLO 100nF INLO V OCM 25Ω Figure 40. ADC Driving Application Using Differential Input R F INHI OPHI 100nF R1 SINGLE- 25Ω ENDED AD8351 50Ω SOURCE OPLO 100nF ...

Page 30

AD6654 input clock cycle, as long as the input signal remains below the lower threshold register value. If the counter reaches 1, the gain control output is incremented the signal goes above the lower threshold register value, ...

Page 31

ADC INPUT PORT MONITOR FUNCTION The AD6654 provides a power monitor function that can monitor the DDC input stream and gather statistics about the received signal in a signal chain. This function block can operate in one of three modes ...

Page 32

AD6654 FROM MEMORY MAP POWER MONITOR DOWN PERIOD REGISTER COUNTER LOAD FROM CLEAR LOAD INPUT POWER MONITOR PORTS ACCUMULATOR Figure 45. ADC Input Mean Power Monitoring Block Diagram THRESHOLD CROSSING MODE Control Bits 10 In this mode of operation, the ...

Page 33

INPUT CROSSBAR MATRIX The AD6654 has one ADC input port and six channels. Each channel can individually select its input source from either the real ADC input port, or from an internally generated pseudo random sequence (referred ...

Page 34

AD6654 NUMERICALLY CONTROLLED OSCILLATOR (NCO) Each channel consists of an independent complex NCO and a complex mixer. This processing stage is comprised of a digital tuner consisting of three multipliers and a 32-bit complex NCO. The NCO serves as a ...

Page 35

If the carrier frequency is 70 MHz and the clock frequency is 80 MHz, then: mod CLK = = . 0 125 f 80 CLK This, in turn, converts to 0xE000 0000 in the ...

Page 36

AD6654 FIFTH-ORDER CIC FILTER The signal processing stage immediately after the NCO is a CIC filter stage. This stage implements a fixed coefficient, decimat- ing, cascade integrated comb filter. The input rate to this filter is the same as the ...

Page 37

EXAMPLE CALCULATIONS Goal: Implement a filter with an input sample rate of 100 MHz requiring 100 dB of alias rejection for a ±1.4 MHz pass band. Solution: First determine the percentage of the sample rate that is represented by the ...

Page 38

AD6654 FIR HALF-BAND BLOCK The output of the CIC filter is pipelined into the FIR HB (half- band) block. Each channel has two sets of cascading fixed coefficient FIR and fixed coefficient half-band filters. The half- band filters decimate by ...

Page 39

The filter has a maximum input sample rate of 150 MHz and, when filter is not bypassed, the maximum output rate is 75 MHz. The filter has a ripple of 0.0012 dB and rejection of 77 dB. For an alias ...

Page 40

AD6654 control register bypasses this fixed coefficient HB filter. The filter is useful only in certain filter configurations and bypassing it for other applications results in power savings. For example, the filter is useful in narrow-band applications in which more ...

Page 41

INTERMEDIATE DATA ROUTER Following the FIR-HB cascade filters is the intermediate data router. This data router consists of muxes that allow the I and Q data from any channel front end (input port + NCO + CIC + FIRHB) to ...

Page 42

AD6654 MONO-RATE RAM COEFFICIENT FILTER (MRCF) The MRCF is a programmable sum-of-products FIR filter. This filter block comes after the first data router and before the DRCF and CRCF programmable filters. It consists of a maxi- mum of eight taps ...

Page 43

DECIMATING RAM COEFFICIENT FILTER (DRCF) Following the MRCF is the programmable DRCF FIR filter. This filter can calculate asymmetrical filter taps 128 symmetrical filter taps. The filter is also capable of a programmable decimation ...

Page 44

AD6654 PROGRAMMING DRCF REGISTERS FOR AN ASYMMETRICAL FILTER To program the DRCF registers for an asymmetrical filter: 1. Write NTAPS – the DRCF taps register, where NTAPS is the number of filter taps. The absolute maximum value for ...

Page 45

CHANNEL RAM COEFFICIENT FILTER (CRCF) Following the DRCF is the programmable decimating CRCF FIR filter. The only difference between the DRCF and CRCF filters is the coefficient bit width. The DRCF has 14-bit coefficients, while the CRCF has 20-bit coefficients. ...

Page 46

AD6654 PROGRAMMING CRCF REGISTERS FOR AN ASYMMETRICAL FILTER To program the CRCF registers for an asymmetrical filter: 1. Write NTAPS – the CRCF taps register, where NTAPS is the number of filter taps. The absolute maximum value for ...

Page 47

INTERPOLATING HALF-BAND FILTER The AD6654 has interpolating half-band FIR filters that immediately follow the CRCF programmable FIR filters and precede the second data router. Each interpolating half-band filter takes 22-bit I and 22-bit Q data from the preceding CRCF and ...

Page 48

AD6654 OUTPUT DATA ROUTER The output data router circuit precedes the six AGCs of the final output block and immediately follows interpolating half- band filters. This block consists of two subblocks. The first block is responsible for combining (interleaving) data ...

Page 49

AUTOMATIC GAIN CONTROL The AD6654 is equipped with six independent automatic gain control (AGC) loops that directly follow the second data router and immediately precede the parallel output ports. Each AGC circuit has range important ...

Page 50

AD6654 DESIRED SIGNAL LEVEL MODE In this mode of operation, the AGC strives to maintain the output signal at a programmable set level. The desired signal level mode is selected by writing Logic 0 into the AGC clipping error enable ...

Page 51

Therefore, in the previous example, if the desired signal level is −13.8 dB, the request level R is programmed to be −16.54 dB, compensating for the offset. This request signal level is programmed in the 8-bit AGC desired level register. ...

Page 52

AD6654 4 exponent plus 8 mantissa bit floating-point representation similar to the error threshold. This is taken as the initial gain value before the AGC loop starts operating. The products of the gain multiplier are the AGC scaled outputs with ...

Page 53

PARALLEL PORT OUTPUT The AD6654 incorporates three independent 16-bit parallel ports for output data transfer. The three parallel output ports share a common clock, PCLK. Each port consists of a 16-bit data bus, request signal, acknowledge signal, three channel indicator ...

Page 54

AD6654 PCLK PxACK PxREQ Px [15:0] PxIQ PxCH [2:0] PxGAIN PCLK PxACK PxREQ Px [15:0] PxIQ PxCH [2:0] PxGAIN When an output data sample is available for output from an AGC, the parallel port initiates the transfer by pulling the ...

Page 55

MASTER/SLAVE PCLK MODES The parallel ports can operate in either master or slave mode. The mode is set via PCLK master mode bit in the Parallel Port Control 2 register. The parallel ports power up in slave mode to avoid ...

Page 56

AD6654 PARALLEL PORT PIN FUNCTIONS Table 25 describes the functions of the pins used by the parallel ports. Table 25. Parallel Port Pin Functions Pin Name I/O Function PCLK I/O Parallel Clock. PCLK can operate as a master or as ...

Page 57

USER-CONFIGURABLE BUILT-IN SELF-TEST (BIST) Each channel of AD6654 includes a BIST block. The BIST, along with an internal test signal (pseudo random test input signal), can be used to generate a signature. This signature can be compared with a known ...

Page 58

AD6654 CHIP SYNCHRONIZATION The AD6654 offers two types of synchronization: start sync and hop sync. Start sync is used to bring individual channels out of sleep after programming. It can also be used while AD6654 is operational to resynchronize the ...

Page 59

NCO. Note: When using SPI or SPORT for programming these registers, the last step in the above procedure needs to be repeated, that is, the soft synchronization ...

Page 60

AD6654 SERIAL PORT CONTROL The AD6654 serial port allows all memory to be accessed (programmed or readback) serially in one-byte words. Either serial port or microport can be used (but not both) at any given time. Serial port control is ...

Page 61

MSBFIRST SCS BLOCK END ADDRESS WR + COUNT (3) SDI 0xaa SDO MODE Figure 61. Serial Write of Three Bytes with MSBFIRST = 1 (All Words are Written MSB first) MSBFIRST SCS BLOCK START ADDRESS SDI 0xaa SDO MODE Figure ...

Page 62

AD6654 MSBFIRST SCS BLOCK START ADDRESS SDI SDO MODE Figure 64. Serial Read of Three Bytes with MSBFIRST = 0 (All Words are Written or Read LSB First) SPI MODE TIMING In SPI mode, the SCLK should run only when ...

Page 63

MSBFIRST SCLK SCS SMODE BLOCK END ADDRESS SDI SDO MODE SPI Read During a typical read operation, a one byte address and one byte instruction are written to the serial port to instruct the internal ...

Page 64

AD6654 MSBFIRST SCLK SCS SMODE BLOCK START ADDRESS SDI SDO MODE SPORT MODE TIMING In SPORT mode, the SCLK continuously runs, and the external SRFS and STFS signals are used to frame the data. Incoming ...

Page 65

MSBFIRST SCLK SCS SMODE SRFS BLOCK START ADDRESS SDI STFS SDO MODE SPORT Read For a typical SPORT read operation, the user must write an address byte and instruction byte to the serial port to ...

Page 66

AD6654 MSBFIRST SCLK SCS SMODE SRFS BLOCK START ADDRESS SDI STFS SDO MODE BLOCK COUNT (Nx Figure 72. SPORT Read MSBFIRST = 0 Rev ...

Page 67

PROGRAMMING INDIRECT ADDRESSED REGISTERS USING SERIAL PORT This section gives examples for programming CRCF coefficient RAM (with an indirect addressing scheme) using the serial port (either SPI or SPORT modes). Though the following specific examples are for CRCF coefficient RAM ...

Page 68

AD6654 LSBFIRST Mode Using Single Byte Block Transfers SerialWrite(0x98); //CRCF Start Address SerialWrite(0x01); SerialWrite(0x00); SerialWrite(0x99); //CRCF Final Address SerialWrite(0x01); SerialWrite(N-1); //N is the number of coefficients for (i < N; i++) { // writing registers SerialWrite(0x9C); //LSB written ...

Page 69

CONNECTING THE AD6654 SERIAL PORT TO A BLACKFIN DSP In SPI mode, the Blackfin DSP must act as a master to the AD6654 by providing the SCLK. SDO is an open-drain output, so that multiple slave devices can be connected ...

Page 70

AD6654 MICROPORT The microport on the AD6654 can be used for programming the part, reading register values, and reading output data (I, Q, and RSSI words). Note that, at any given point in time, either the microport or the serial ...

Page 71

ACCESSING MULTIPLE AD6654 DEVICES If multiple AD6654 devices are on a single board, the microport pins for these devices can be shared. In this configuration, a single programming device (DSP, FPGA, or microcontroller) can program all AD6654 devices connected to ...

Page 72

AD6654 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has four address locations. The memory map is roughly divided into four regions: global register map (Address 0x00 to Address 0x0B), input port register map ...

Page 73

Table 28. Memory Map 8-Bit Hex Address Byte 3 0x03 Open <7:6>, Channel Enable <5:0> 0x07 Open <15:11>, Reserved <10:0> (default 0x06FC) 0x0B Interrupt Mask <15:0> ADC Input Port Register Map— Addresses 0x0C to 0x57 0x0F ADC Input Control <31:0> ...

Page 74

AD6654 GLOBAL REGISTER MAP Chip I/O Access Control Register <7:0> <7>: Synchronous Microport Bit. When this bit is set, the microport assumes that its control signals (such and CS ,) are synchronous to the ...

Page 75

Enable Synchronization from SYNC2 Bit. Similar to Bit <3> for the SYNC2 pin. <1>: Enable Synchronization from SYNC1 Bit. Similar to Bit <3> for the SYNC1 pin. <0>: Enable Synchronization from SYNC0 Bit. Similar to Bit <3> for the ...

Page 76

AD6654 Interrupt Enable Register <15:0> <15>: AGC5 RSSI Update Enable Bit. When this bit is set, the AGC5 RSSI update interrupt is enabled, allowing an interrupt to be generated when the RSSI word is updated. When this bit is cleared, ...

Page 77

ADC Port CLK Invert Bit. When this bit is set, the inverted ADC port clock is used to register ADC input data into the part. When this bit is cleared, the clock is used as is, without any inversion ...

Page 78

AD6654 <2:1>: Monitor Function Select Bits. Table 32 describes the function of these bits. Table 32. Monitor Function Select Bits Monitor Function Select Function Enabled 00 Peak detect mode 01 Mean power monitor mode 10 Threshold crossing mode 11 Invalid ...

Page 79

CIC Decimation <4:0> This 5-bit word specifies the CIC filter decimation value minus 1. A value of 0x00 is a decimation of 1 (bypass), and 0x1F is a decimation of 32. Writing a value this register bypasses ...

Page 80

AD6654 Table 37. DRCF Multiply Accumulate Scale Bits DRCF Scale <1:0> Scale Factor 00 18.06 dB attenuation (left-shift 3 bits) 01 12.04 dB attenuation (left-shift 2 bits) 10 6.02 dB attenuation (left-shift 1 bit scaling (0 dB) <7:4>: ...

Page 81

CRCF Coefficient Memory CRCF Memory. This memory has 64 words that have 20 bits each. The memory contains the CRCF filter coefficients. The data written to this memory space is 20-bit in twos complement format. See the Channel RAM Coefficient ...

Page 82

AD6654 format of the AGC error threshold register is four bits to the left of the binary point and eight bits to the right. See the Automatic Gain Control section for details. ⎡ Error Threshold = ⎢ Register Value round ...

Page 83

When this bit is cleared, AGC5 data does not appear on Output Port C. <20>: Port C, AGC4 Enable Bit. Similar to Bit 21 for AGC4. <19>: Port C, AGC3 Enable Bit. Similar to Bit 21 for AGC3. <18>: Port ...

Page 84

AD6654 AGC0, I Output <15:0> This read-only register provides the latest in-phase output sample from AGC0. Note that AGC0 might be bypassed, and that AGC0 here is representative of the datapath only. AGC0, Q Output <15:0> This read-only register provides ...

Page 85

DDC DESIGN NOTES The following guidelines describe circuit connections, layout requirements, and programming procedures for the AD6654. The designer should review these guidelines before starting the system design and layout. • The AD6654 requires the following power-up sequence. The VDDCORE ...

Page 86

AD6654 • In the Intel mode microport, the beginning of a read and write access is indicated by the RDY pin going low. The access is complete only when the RDY pin goes high. In the Motorola mode microport, the ...

Page 87

... ORDERING GUIDE Model Temperature Range AD6654BBC −25°C to +85°C 1 AD6654BBCZ −25°C to +85°C AD6654CBC −25°C to +85°C 1 AD6654CBCZ −25°C to +85°C AD6654/PCB Pb-free part. 17.20 17. 16.80 BALL A1 CORNER 15.00 BSC SQ TOP VIEW 1.00 BSC DETAIL A ...

Page 88

AD6654 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05156–0–4/05(0) Rev Page ...

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