AD6654/PCB Analog Devices Inc, AD6654/PCB Datasheet - Page 49

• Manufacturer Part Number: AD6654/PCB
• Description: BOARD EVALUATION FOR AD6654
• Manufacturer: Analog Devices Inc

Specifications of AD6654/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6554
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AUTOMATIC GAIN CONTROL
The AD6654 is equipped with six independent automatic gain
control (AGC) loops that directly follow the second data router
and immediately precede the parallel output ports. Each AGC
circuit has 96 dB of range. It is important that the decimating
filters of the AD6654 preceding the AGC reject unwanted
signals, so that each AGC loop is operating only on the carrier
of interest, and carriers at other frequencies do not affect the
ranging of the loop.
The AGC compresses the 22-bit complex output from the
second data router into a programmable word size of 4 to 8, 10,
12, or 16 bits. Because the small signals from the lower bits are
pushed in to higher bits by adding gain, the clipping of the
lower bits does not compromise the SNR of the signal of
interest.
The AGC maintains a constant mean power on the output
despite the level of the signal of interest, allowing operation in
environments where the dynamic range of the signal exceeds
the dynamic range of the output resolution. The output width of
the AGC is set by writing a 3-bit AGC word-length word in the
AGC control register of the individual channel’s memory map.
The AGC can be bypassed, if needed, and, when bypassed, the
24-bit complex input word remains truncated to a 16-bit value
that is output through the parallel port output. The six AGCs
available on the AD6654 are programmable through the six
channel memory maps. AGCs corresponding to individual
channels can be bypassed by writing Logic 1 to the AGC bypass
bit in the AGC control register.
Three sources of error can be introduced by the AGC function:
underflow, overflow, and modulation. Underflow is caused by
Q
I
G (z) =
BITS
22
1 – (1 + )
POWER OF 2
2×
P
Kz
z
–1
GAIN MULTIPLIER
–1
+ Pz
–2
E ERROR
THRESHOLD
Figure 56. Block Diagram of the AGC
Rev. 0 | Page 49 of 88
K1 GAIN
K2 GAIN
P POLE
AVERAGE 1 – 16384 SAMPLES
DECIMATE 1 – 4096 SAMPLES
MEAN SQUARE (I
ERROR
SQUARE ROOT
log
truncation of bits below the output range. Overflow is caused by
clipping errors when the output signal exceeds the output range.
Modulation error occurs when the output gain varies while
receiving data.
The desired signal level should be set based on the probability
density function of the signal, so that the errors due to under-
flow and overflow are balanced. The gain and damping values
of the loop filter should be set, so that the AGC is fast enough to
track long-term amplitude variations of the signal that might
cause excessive underflow or overflow, but slow enough to
avoid excessive loss of amplitude information due to the
modulation of the signal.
AGC LOOP
The AGC loop is implemented using a log-linear architecture. It
contains four basic operations: power calculation, error calcula-
tion, loop filtering, and gain multiplication.
The AGC can be configured to operate in either desired signal
level mode or desired clipping level mode. The mode is set by
the AGC clipping error bit of the AGC control register. The
AGC adjusts the gain of the incoming data according to how far
it is from a given desired signal level or desired clipping level,
depending on the selected mode of operation.
Two data paths to the AGC loop are provided: one before the
clipping circuitry and one after the clipping circuitry, as shown
in Figure 56. For the desired signal level mode, only the I/Q
path prior to the clipping is used. For the desired clipping level
mode, the difference of the I/Q signals from before and after the
clipping circuitry is used.
2
CLIP
CLIP
(x)
R DESIRED
2
+ Q
PROGRAMMABLE
2
)
BIT WIDTH
USED ONLY FOR
DESIRED CLIPPING
LEVEL MODE
Q
I
AD6654