M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 58

• Manufacturer Part Number: M306N5FCTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N5FCTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
7.2 Bus Control
Figure 7.1 CSR Register
The following describes the signals needed for accessing external devices and the functionality of software
wait.
7.2.1 Address Bus
7.2.2 Data Bus
7.2.3 Chip Select Signal
The address bus consists of 20 lines, A0 to A19.
The address bus width can be chosen to be 12,
16 or 20 bits by using the PM06 bit in the PM0
register and the PM11 bit in the PM1 register.
Table 7.2 shows Bits PM06 and PM11 Set Values
and Address Bus Widths.
When processor mode is changed from single-chip
mode to memory expansion mode, the address
bus is undefined until any external area is
accessed.
When input on the BYTE pin is high (data bus is an 8-bit width), 8 lines D0 to D7 comprise the data bus;
when input on the BYTE pin is low (data bus is a 16-bit width), 16 lines D0 to D15 comprise the data bus.
Do not change the input level on the BYTE pin while in operation.
The chip select (hereafter referred to as the CS) signals are output from the CSi (i = 0 to 3) pins. These
pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.
Figure 7.1 shows the CSR Register.
During 1 Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output
from the CSi pin.
Figure 7.2 shows the Example of Address Bus and CSi Signal Output.
Chip Select Control Register
NOTES:
b7
Apr 14, 2006
1. Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplexed bus is used, set the
2. If the PM17 bit in the PM1 register is set to 1 (with wait state), set the CSiW bit to 0 (with wait state).
3. When the CSiW bit = 0 (with wait state), the number of wait states (in terms of clock cycles) can be selected
b6
CSiW bit to 0 (wait state).
using bits CSEi1W to CSEi0W in the CSE register.
b5
______
b4
b3
b2
page 36 of 372
b1
b0
Bit Symbol
CS0W
CS1W
CS2W
CS3W
CS0
CS1
CS2
CS3
Symbol
CSR
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
_____
Bit Name
Address
_____
0008h
______
Table 7.2 Bits PM06 and PM11 Set Value and
NOTE:
PM11 = 1
PM06 = 1
PM11 = 0
PM06 = 1
PM11 = 0
PM06 = 0
Set Value
1. No values other than those shown above can
be set.
Address Bus Width
(1)
0 : Chip select output disabled
1 : Chip select output enabled
0 : With wait state
1 : Without wait state
After Reset
00000001b
(functions as I/O port)
P3_4 to P3_7 12 bits
P4_0 to P4_3
A12 to A15
P4_0 to P4_3
A12 to A15
A16 to A19
Pin Function Address Bus Width
Function
______
______
(1) (2) (3)
16 bits
20 bits
RW
RW
RW
RW
RW
RW
RW
RW
RW
7. Bus