M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 113

• Manufacturer Part Number: M306N5FCTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N5FCTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Table 12.1 DMAC Specifications
i = 0, 1
NOTES:
No. of channels
Transfer memory space
Maximum no. of bytes transferred 128 Kbytes (with 16-bit transfer) or 64 Kbytes (with 8-bit transfer)
DMA request sources
Channel priority
Transfer unit
Transfer address direction
Transfer mode Single transfer
DMA interrupt request
generation timing
DMA start up
DMA shutdown Single transfer
Reload timing for forward
address pointer and transfer
counter
DMA transfer cycles
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
2. The selectable DMA request sources differ with each channel.
3. Make sure that no DMAC-related registers (addresses 0020h to 003Fh) are accessed by the DMAC.
interrupt control register.
Apr 14, 2006
Item
Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value
Repeat transfer When the DMAE bit is set to 0 (disabled)
page 91 of 372
(1) (2)
2 (cycle steal method)
• From given address in the 1-Mbyte space to a fixed address
• From a fixed address to given address in the 1-Mbyte space
• From a fixed address to a fixed address
Falling edge of INT0 or INT1
Both edge of INT0 or INT1
Timers A0 to A4 interrupt requests
Timers B0 to B5 interrupt requests
UART0 transmit, UART0 receive interrupt requests
UART1 transmit, UART1 receive interrupt requests
UART2 transmit, UART2 receive interrupt requests
SI/O3 interrupt request
A/D conversion interrupt requests
Software triggers
DMA0 > DMA1 (DMA0 takes precedence)
8 bits or 16 bits
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer is completed when the DMAi transfer counter underflows
after reaching the terminal count.
of the DMAi transfer counter reload register and a DMA transfer is
continued with it.
When the DMAi transfer counter underflowed
Data transfer is initiated each time a DMA request is generated when the
The DMAE bit in the DMAiCON register = 1 (enabled).
• When the DMAE bit is set to 0 (disabled)
• After the DMAi transfer counter underflows
When a data transfer is started after setting the DMAE bit to 1 (enabled),
the forward address pointer is reloaded with the value of the SARi or the
DARi pointer whichever is specified to be in the forward direction and the
DMAi transfer counter is reloaded with the value of the DMAi transfer
counter reload register.
Minimum 3 cycles between SFR and internal RAM
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Specification
12. DMAC