M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 179

• Manufacturer Part Number: M306N5FCTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N5FCTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Figure 15.17 Transmit Operation
(1) 8-bit data transmit timing (with a parity and 1 stop bit)
(2) 9-bit data transmit timing (with no parity and 2 stop bits)
Transfer Clock
TE bit in UiC1
register
TI bit in UiC1
register
TXDi
TXEPT bit in
UiC0 register
IR bit in
SiTIC register
Transfer Clock
TE bit in UiC1
register
TI bit in UiC1
register
CTSi
TXDi
TXEPT bit in
UiC0 register
IR bit in
SiTIC register
i = 0 to 2
The above timing diagram applies to the case where the register bits are
set as follows:
i = 0 to 2
The above timing diagram applies to the case where the register bits are
set as follows:
PRYE bit in UiMR register = 1 (parity enabled)
STPS bit in UiMR register = 0 (1 stop bit)
CRD bit in UiC0 register = 0 (CTS/RTS enabled) and
CRS bit in UiC0 register = 0 (CTS selected)
UiIRS bit = 1 (an interrupt request is generated when transmission completed):
PRYE bit in UiMR register = 0 (parity disabled)
STPS bit in UiMR register = 1 (2 stop bits)
CRD bit in UiC0 register = 1 (CTS/RTS disabled)
UiIRS bit = 0 (an interrupt request is generated when transmit buffer becomes empty):
Apr 14, 2006
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
1
0
1
0
1
0
1
0
"H"
"L"
1
0
1
0
1
0
1
0
page 157 of 372
Start bit
ST
Start bit
Data is set to the UiTB register
D0
ST
D1
D0
Set to 0 by an interrupt request acknowledgement or by program
Data is set to the UiTB register
D2
D1
TC
D3
D2
TC
D4
D3
D5
D4
Data is transferred from the UiTB register to the UARTi transmit register
D6
D5
The transfer clock stops momentarily, because an "H" signal is applied to the CTS pin,
when the stop bit is verified.
The transfer clock resumes running as soon as an "L" signal is applied to the CTS pin.
D7
D6
Stop
D8
D7
bit
Data is transferred from the UiTB register to
the UARTi transmit register
Parity
SP
bit
P
Set to 0 by an interrupt request acknowledgement or by program
SP
SP
Stop
Stop
ST
ST
bit
bit
D0
D0
TC = 16(n+1) / fj or 16(n+1) / fEXT
TC = 16(n+1) / fj or 16(n+1) / fEXT
D1
D1
fj: frequency of UiBRG count source
fEXT: frequency of UiBRG count source (external clock)
n: value set to the UiBRG register
fj: frequency of UiBRG count source
fEXT: frequency of UiBRG count source (external clock)
n: value set to the UiBRG register
D2
D2
(f1SIO, f2SIO, f8SIO, f32SIO)
(f1SIO, f2SIO, f8SIO, f32SIO)
D3
D3
D4
D4
Pulse stops because the TE bit is set to 0
D5
D5
D6
D6
D7
D7
D8
P
SP
SP SP
15. Serial Interface
ST
ST
D0
D0
D1
D1