M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 171

• Manufacturer Part Number: M306N5FCTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N5FCTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Figure 15.11 Transmit and Receive Operation
i = 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
i = 0 to 2
The above timing diagram applies to the case where the register bits are set
as follows:
fEXT: frequency of external clock
(1) Example of transmit timing (when internal clock is selected)
(2) Example of receive timing (when external clock is selected)
TE bit in
UiC1 register
TI bit in
UiC1 register
CTSi
CLK
TXDi
TXEPT bit in
UiC0 register
IR bit in
SiTIC register
RE bit in
UiC1 register
TE bit in
UiC1 register
TI bit in
UiC1 register
RTSi
CLKi
RXDi
RI bit in
UiC1 register
IR bit in
SiRIC register
OER flag in UiRB
register
Transfer clock
CKDIR bit in UiMR register = 0 (internal clock)
CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit in UiC0 register = 0 (CTS selected)
CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data
UiIRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty):
CKDIR bit in UiMR register = 1 (external clock)
CRD bit in UiC0 register = 0 (CTS/RTS enabled),
CRS bit in UiC0 register = 1 (RTS selected)
CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and
Apr 14, 2006
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
i
"H"
"L"
1
0
1
0
1
0
1
0
1
0
1
0
"H"
"L"
1
0
1
0
1
0
1
0
receive register to the UiRB register
page 149 of 372
Data is transferred from UARTi
D0 D1 D2 D3 D4 D5 D6 D7
Data is set to the UiTB register
Dummy data is set to the UiTB register
taken in at the rising edge of the transfer clock)
D0 D1 D2 D3 D4 D5 D6 D7
receive data taken in at the rising edge of
the transfer clock)
Set to 0 by an interrupt request acknowledgement or by program
Data is transferred from the UiTB register to the UARTi transmit register
TCLK
Data is transferred from the UiTB register to the UARTi transmit register
1 / f
Receive data is taken in
TC
EXT
Pulse stops because an "H" signal is
applied to CTSi
D0 D1 D2 D3 D4 D5
Set to 0 by an interrupt request acknowledgement or by program
Read by the UiRB register
An "L" signal is applied when
the UiRB register is read
D0 D1 D2 D3 D4 D5 D6 D7
Make sure the following conditions are met when input
to the CLKi pin before receiving data is high:
TE bit in UiC1 register = 1 (transmission enabled)
RE bit in UiC1 register = 1 (reception enabled)
Write dummy data to the UiTB register
D6
D7
TC = TCLK = 2(n + 1) / fj
D0 D1 D2 D3 D4 D5
Pulse stops because the TE bit is set to 0
fj: frequency of UiBRG count source
n: value set to the UiBRG register
(f1SIO, f2SIO, f8SIO, f32SIO)
D0 D1 D2 D3 D4 D5 D6 D7
15. Serial Interface
D6