M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 405
M306N5FCTFP
Manufacturer Part Number
M306N5FCTFP
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M306N5FCTFPUK.pdf
(90 pages)
3.M306N5FCTFPU0.pdf
(408 pages)
Specifications of M306N5FCTFP
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
87
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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2.40 Apr.14, 2006
Rev.
Date
REVISION HISTORY
137, 138 Figures 15.1 to 15.3 are revised.
Page
129
133
140
141
146
149
154
157
158
162
164
171
178
180
182
184
185
186
187
206
215
220
221
222
225
245
284
307
Figure 14.4 Registers IDB0 and IDB1 (upper): The value of After Reset is revised.
Figure 14.8 Registers TA1MR, TA2MR, TA4MR (upper): Note 1 is added.
Figure 14.8 TB2MR Register (lower): Note 1 is added.
Figure 15.5 Registers U0RB to U2RB (middle): Note 3 is added.
Figure 15.6 Registers U0C0 to U2C0 (lower): Note 6 is added.
Table 15.1 Clock Synchronous Serial I/O Mode Specifications
Figure 15.11 Transmit and Receive Operation is revised.
Table 15.5 UART Mode Specifications
Figure 15.17 Transmit Operation is revised.
Table 15.9 Example of Bit Rates and Settings: “Actual Time” is revised to “Bit Rate”.
Table 15.10 I
Table 15.11 Registers to Be Used and Settings in I
Table 15.14 Special Mode 2 Specifications
Table 15.17 SIM Mode Specifications
Figure 15.32 Transmit and Receive Timing in SIM Mode is revised.
15.1.6.2 Format is revised.
Figure 15.37 S3C Register (upper): Note 6 is added.
Table 15.19 SI/O3 Specifications
Figure 15.38 SI/O3 Operation Timing: Cycle and Note 1 is revised. (1.5 -> 0.5 to 1.0)
15.2.3 Functions for Setting SOUT3 Initial Value: 2nd item (However...) is added.
Figure 17.3 D/A Converter Equivalent Circuit is revised.
Figure 19.7 C0CTLR Register (upper): NOTE 4 is added.
Figure 19.12 C0TSR Register (3rd register): Note 1 is added.
Figure 19.13 Transition between Operational Modes is revised.
19.5.3 CAN Sleep Mode
Table 19.2 Examples of Bit-rate is revised.
Table 20.2 Unassigned Pin Handling in Memory expansion Mode and Microprocessor Mode
Table 22.4 Electrical Characteristics (1): Hysteresis XIN is deleted.
Table 22.32 Electrical Characteristics (1): Hysteresis XIN is deleted.
• Transfer clock: “fj/2(n+1)” is revised to “fj/(2(n+1))”.
• Note 3 is revised.
• Transfer clock: “fj/16(n+1)” is revised to “fj/(16(n+1))” and “fEXT/16(n+1)” is revised
• Note 2 is revised.
• Transfer clock: “fj/2(n+1)” is revised to “fj/(2(n+1))”.
• Transfer clock: “fj/2(n+1)” is revised to “fj/(2(n+1))”.
• Transfer clock: “fj/16(n+1)” is revised to “fj/(16(n+1))” and “fEXT/16(n+1)” is revised
• Transfer clock: “fj/2(n+1)” is revised to “fj/(2(n+1))”.
• 1st item: “and Reset bit to 0” is deleted.
• Pin Name: “P0 to P7” is revised to “P6, P7”.
to “fEXT/(16(n+1))” .
to “fEXT/(16(n+1))”.
2
C Mode Specifications
M16C/6N Group (M16C/6N5) Hardware Manual
C-11
Description
Summary
2
C Mode: Note 3 is added.
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