M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 195

IC M16C MCU FLASH 100QFP

M306N5FCTFP

Manufacturer Part Number
M306N5FCTFP
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Datasheets

Specifications of M306N5FCTFP

Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
87
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Table 15.15 Registers to Be Used and Settings in Special Mode 2
i = 0 to 2
NOTES:
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
UCON
Register
1. Not all register bits are described above. Set those bits to 0 when writing to the registers in Special
2. Set bits 4 and 5 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in the
Mode 2.
UCON register.
(1)
(1)
(1)
Apr 14, 2006
0 to 7
0 to 7
OER
SMD2 to SMD0
CKDIR
IOPOL
CLK1 to CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM
UiLCH, UiERE
CKPH
NODC
0, 2, 4 to 7
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1, RCSP, 7 Set to 0
0 to 7
0 to 7
0 to 7
0 to 7
(2)
Bit
(2)
page 173 of 372
,
Set transmit data
Receive data can be read
Overrun error flag
Set a bit rate
Set to 001b
Set this bit to 0 for master mode or 1 for slave mode
Set to 0
Select the count source for the UiBRG register
Invalid because the CRD bit = 1
Transmit register empty flag
Set to 1
Select TXDi pin output format
Clock phases can be set in combination with the CKPH bit in the UiSMR3 register
Set to 0
Set this bit to 1 to enable transmission
Transmit buffer empty flag
Set this bit to 1 to enable reception
Reception complete flag
Select the UART2 transmit interrupt source
Set to 0
Set to 0
Set to 0
Clock phases can be set in combination with the CKPOL bit in the UiC0 register
Set to 0
Set to 0
Set to 0
Select the UART0 and UART1 transmit interrupt source
Set to 0
Invalid because the CLKMD1 bit = 0
Function
15. Serial Interface

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