M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 204
![IC M16C MCU FLASH 100QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
M306N5FCTFP
Manufacturer Part Number
M306N5FCTFP
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M306N5FCTFPUK.pdf
(90 pages)
3.M306N5FCTFPU0.pdf
(408 pages)
Specifications of M306N5FCTFP
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
87
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Figure 15.35 SIM Interface Format
15.1.6.2 Format
When direct format, set the PRYE bit in the U2MR register to 1, the PRY bit to 1, the UFORM bit in the
U2C0 register to 0 and the U2LCH bit in the U2C1 register to 0. When data are transmitted, data set in
the U2TB register are transmitted with the even-numbered parity, starting from D0. When data are
received, received data are stored in the U2RB register, starting from D0. The even-numbered parity
determines whether a parity error occurs.
When inverse format, set the PRYE bit to 1, the PRY bit to 0, the UFORM bit to 1 and the U2LCH bit to
1. When data are transmitted, values set in the U2TB register are logically inversed and are transmitted with
the odd-numbered parity, starting from D7. When data are received, received data are logically inversed
to be stored in the U2RB register, starting from D7. The odd-numbered parity determines whether a
parity error occurs.
Figure 15.35 shows the SIM Interface Format.
Apr 14, 2006
(1) Direct format
(2) Inverse format
Transfer
Transfer
TXD2
TXD2
clock
clock
page 182 of 372
"H"
"H"
"H"
"H"
"L"
"L"
"L"
"L"
D0
D7
D1
D6
D5
D2
D3
D4
D4
D3
D2
D5
D6
D1
D7
D0
P
P
P : Even parity
P : Odd parity
15. Serial Interface
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