M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 200

• Manufacturer Part Number: M306N5FCTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N5FCTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Table 15.17 SIM Mode Specifications
NOTES:
Transfer data format
Transfer clock
Transmit start condition
Receive start condition
Error detection
15.1.6 Special Mode 4 (SIM Mode) (UART2)
Interrupt request
generation timing
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows to output a low from the TXD2 pin when a parity error is detected.
Table 15.17 lists the SIM Mode Specifications. Table 15.18 lists the Registers to be Used and Settings in
SIM Mode. Figure 15.32 shows the Transmit and Receive Riming in SIM Mode.
1. If an overrun error occurs, the value of the U2RB register will be undefined. The IR bit in the S2RIC
2. A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to 1 (transmission
3. The timing at which the framing error flag and the parity error flag are set is detected when data is
register remains unchanged.
completed) and U2ERE bit in the U2C1 register to 1 (error signal output) after reset. Therefore, when
using SIM mode, set the IR bit to 0 (interrupt not requested) after setting these bits.
transferred from the UARTi receive register to the UiRB register.
Apr 14, 2006
Item
(2)
page 178 of 372
• Direct format
• Inverse format
• The CKDIR bit in the U2MR register = 0 (internal clock) : fi/(16(n+1))
• The CKDIR bit = 1 (external clock) : fEXT/(16(n+1))
Before transmission can start, meet the following requirements
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)
Before reception can start, meet the following requirements
• The RE bit in the U2C1 register = 1 (reception enabled)
• Start bit detection
• For transmission
• For reception
• Overrun error
• Framing error
• Parity error
• Error sum flag
fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the U2BRG register 00h to FFh
fEXT: Input from CLK2 pin.
When the serial interface finished sending data from the U2TB transfer register
(U2IRS bit = 1)
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
This error occurs if the serial interface started receiving the next data before reading
the U2RB register and received the bit one before the last stop bit of the next data
This error occurs when the number of stop bits set is not detected
During reception, if a parity error is detected, parity error signal is output from the
TXD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
This flag is set to 1 when any of the overrun, framing, and parity errors is encountered
(3)
(1)
(3)
n: Setting value of the U2BRG register
Specification
15. Serial Interface
00h to FFh