MC68HC711D3CFNE2 Freescale Semiconductor, MC68HC711D3CFNE2 Datasheet - Page 75
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MC68HC711D3CFNE2
Manufacturer Part Number
MC68HC711D3CFNE2
Description
IC MCU 8BIT 3MHZ 44-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MC68HC711D3CFNE2
Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
26
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC711D3CFNE2
Manufacturer:
ALLEGEO
Quantity:
4 492
Company:
Part Number:
MC68HC711D3CFNE2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Status Flags and Interrupts
6.8 Status Flags and Interrupts
The SCI transmitter has two status flags. These status flags can be read by software (polled) to tell when
the corresponding condition exists. Alternatively, a local interrupt enable bit can be set to enable each of
these status conditions to generate interrupt requests when the corresponding condition is present.
Status flags are automatically set by hardware logic conditions, but must be cleared by software, which
provides an interlock mechanism that enables logic to know when software has noticed the status
indication. The software clearing sequence for these flags is automatic — functions that are normally
performed in response to the status flags also satisfy the conditions of the clearing sequence.
TDRE and TC flags are normally set when the transmitter is first enabled (TE set to 1). The TDRE flag
indicates there is room in the transmit queue to store another data character in the TDR. The TIE bit is
the local interrupt mask for TDRE. When TIE is 0, TDRE must be polled. When TIE and TDRE are 1, an
interrupt is requested.
The TC flag indicates the transmitter has completed the queue. The TCIE bit is the local interrupt mask
for TC. When TCIE is 0, TC must be polled; when TCIE is 1 and TC is 1, an interrupt is requested.
Writing a 0 to TE requests that the transmitter stop when it can. The transmitter completes any
transmission in progress before actually shutting down. Only an MCU reset can cause the transmitter to
stop and shut down immediately. If TE is written to 0 when the transmitter is already idle, the pin reverts
to its general-purpose I/O function (synchronized to the bit-rate clock). If anything is being transmitted
when TE is written to 0, that character is completed before the pin reverts to general-purpose I/O, but any
other characters waiting in the transmit queue are lost. The TC and TDRE flags are set at the completion
of this last character, even though TE has been disabled.
The SCI receiver has five status flags, three of which can generate interrupt requests. The status flags
are set by the SCI logic in response to specific conditions in the receiver. These flags can be read (polled)
at any time by software. Refer to
Figure
6-9, which shows SCI interrupt arbitration.
When an overrun takes place, the new character is lost, and the character that was in its way in the
parallel RDR is undisturbed. RDRF is set when a character has been received and transferred into the
parallel RDR. The OR flag is set instead of RDRF if overrun occurs. A new character is ready to be
transferred into RDR before a previous character is read from RDR.
The NF and FE flags provide additional information about the character in the RDR, but do not generate
interrupt requests.
The last receiver status flag and interrupt source come from the IDLE flag. The RxD line is idle if it has
constantly been at logic 1 for a full character time. The IDLE flag is set only after the RxD line has been
busy and becomes idle, which prevents repeated interrupts for the whole time RxD remains idle.
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
75