MC68HC711D3CFNE2 Freescale Semiconductor, MC68HC711D3CFNE2 Datasheet - Page 59

• Manufacturer Part Number: MC68HC711D3CFNE2
• Description: IC MCU 8BIT 3MHZ 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711D3CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 26
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

PSEL3–PSEL0 — Priority Selects
Freescale Semiconductor
These four bits are used to specify one I bit related interrupt source, which then becomes the highest
priority I bit related interrupt source. These bits may be written only while the I bit in the CCR is set,
inhibiting I bit related interrupts. An interpretation of the value of these bits is shown in
During reset, PSEL3–PSEL0 are initialized to 0101, which corresponds to reserved (default to IRQ).
IRQ becomes the highest priority I bit related interrupt source.
To prevent bus conflicts, when using internal read visibility, the user must
disable all external devices from driving the data bus during any internal
access.
PSEL3–PSEL0
Single chip
Expanded multiplexed
Bootstrap
Special test
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Mode
Table 4-4. Highest Priority Interrupt Selection
Timer overflow
Pulse accumulator overflow
Pulse accumulator input edge
SPI serial transfer complete
SCI serial system
Reserved (default to IRQ)
IRQ (external pin)
Real-time interrupt
Timer input capture 1
Timer input capture 2
Timer input capture 3
Timer output compare 1
Timer output compare 2
Timer output compare 3
Timer output compare 4
Timer input capture 4/output compare 5
MC68HC711D3 Data Sheet, Rev. 2.1
of Reset
IRVNE
Out
0
0
0
1
of Reset
NOTE
E Clock
Interrupt Source Promoted
Out
On
On
On
On
of Reset
Out
IRV
Off
Off
Off
On
Affects
IRVNE
Only
IRV
IRV
E
E
be Written
IRVNE
Once
Once
Once
Once
May
Table
Interrupts
4-4.
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