MC68HC711D3CFNE2 Freescale Semiconductor, MC68HC711D3CFNE2 Datasheet - Page 71

IC MCU 8BIT 3MHZ 44-PLCC

MC68HC711D3CFNE2

Manufacturer Part Number
MC68HC711D3CFNE2
Description
IC MCU 8BIT 3MHZ 44-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711D3CFNE2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
26
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC711D3CFNE2
Manufacturer:
ALLEGEO
Quantity:
4 492
Part Number:
MC68HC711D3CFNE2
Manufacturer:
FREESCALE
Quantity:
1 489
Part Number:
MC68HC711D3CFNE2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
ILIE — Idle Line Interrupt Enable Bit
TE — Transmitter Enable Bit
RE — Receiver Enable Bit
RWU — Receiver Wakeup Control Bit
SBK — Send Break Bit
6.7.4 SCI Status Register
The SCI status register (SCSR) provides inputs to the interrupt logic circuits for generation of the SCI
system interrupt.
TDRE — Transmit Data Register Empty Flag
TC — Transmit Complete Flag
RDRF — Receive Data Register Full Flag
Freescale Semiconductor
When TE goes from 0 to 1, one unit of idle character time (logic 1) is queued as a preamble.
At least one character time of break is queued and sent each time SBK is written to 1. More than one
break may be sent if the transmitter is idle at the time the SBK bit is toggled on and off, as the baud
rate clock edge could occur between writing the 1 and writing the 0 to SBK.
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and then
writing to SCDR.
This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress).
Clear the TC flag by reading SCSR with TC set and then writing to SCDR.
This flag is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading
SCSR with RDRF set and then reading SCDR.
1 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
0 = Transmitter disabled
1 = Transmitter enabled
0 = Receiver disabled
1 = Receiver enabled
0 = Normal SCI receiver
1 = Wakeup enabled and receiver interrupts inhibited
0 = Break generator off
1 = Break codes generated as long as SBK = 1
0 = SCDR busy
1 = SCDR empty
0 = Transmitter busy
1 = Transmitter idle
0 = SCDR empty
1 = SCDR full
Address:
Reset:
Read:
Write:
$002E
TDRE
Bit 7
1
Figure 6-6. SCI Status Register (SCSR)
TC
6
1
MC68HC711D3 Data Sheet, Rev. 2.1
RDRF
5
0
IDLE
4
0
OR
3
0
NF
2
0
FE
1
0
Bit 0
0
0
SCI Registers
71

Related parts for MC68HC711D3CFNE2