MC68HC711D3CFNE2 Freescale Semiconductor, MC68HC711D3CFNE2 Datasheet - Page 100

• Manufacturer Part Number: MC68HC711D3CFNE2
• Description: IC MCU 8BIT 3MHZ 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711D3CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 26
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Programmable Timer
DDRA7 — Data Direction Control for Port A Bit 7
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
PEDGE — Pulse Accumulator Edge Control Bit
DDRA3 — Data Direction Register for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare 5 Bit
RTR1 and RTR0 — RTI Interrupt Rate Select Bits
8.6 Computer Operating Properly Watchdog Function
The clocking chain for the COP function, tapped off of the main timer divider chain, is only superficially
related to the main timer system. The CR1 and CR0 bits in the OPTION register and the NOCOP bit in
the CONFIG register determine the status of the COP function. Refer to
Low-Power Modes
8.7 Pulse Accumulator
The MC68HC711D3 has an 8-bit counter that can be configured to operate either as a simple event
counter or for gated time accumulation, depending on the state of the PAMOD bit in the PACTL register.
Refer to the pulse accumulator block diagram,
In the event counting mode, the 8-bit counter is clocked to increasing values by an external pin. The
maximum clocking rate for the external event counting mode is the E clock divided by two. In gated time
accumulation mode, a free-running E-clock ÷ 64 signal drives the 8-bit counter, but only while the external
PAI pin is activated. Refer to
Pulse accumulator control bits are also located within two timer registers, TMSK2 and TFLG2, as
described here.
100
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
These two bits determine the rate at which the RTI system requests interrupts. The RTI system is
driven by an E divided by 2
These two control bits select an additional division factor. See
8.7 Pulse
8.7 Pulse
8.7 Pulse
8.7 Pulse
Chapter 5 Input/Output (I/O)
8.3 Input
and RTR0
RTR1
for a more detailed discussion of the COP function.
0 0
0 1
1 0
1 1
Capture.
Accumulator.
Accumulator.
Accumulator.
Accumulator.
Table
13
rate clock that is compensated so it is independent of the timer prescaler.
E = 1 MHz
10.923 ms
21.845 ms
2.731 ms
5.461 ms
Table 8-6. Real-Time Interrupt Rates
8-7. The pulse accumulator counter can be read or written at any time.
MC68HC711D3 Data Sheet, Rev. 2.1
Ports.
Figure
E = 2 MHz
16.384 ms
32.768 ms
4.096 ms
8.192 ms
8-19.
E = 3 MHz
16.384 ms
32.768 ms
65.536 ms
8.192 ms
Table
Chapter 4 Resets, Interrupts, and
8-6.
E = X MHz
(E/2
(E/2
(E/2
(E/2
Freescale Semiconductor
13
14
15
16
)
)
)
)