MC68HC711D3CFNE2 Freescale Semiconductor, MC68HC711D3CFNE2 Datasheet - Page 58

• Manufacturer Part Number: MC68HC711D3CFNE2
• Description: IC MCU 8BIT 3MHZ 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711D3CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 26
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Resets, Interrupts, and Low-Power Modes
4.3.6 Highest Priority I Interrupt and Miscellaneous Register (HPRIO)
Four bits of this register (PSEL3–PSEL0) are used to select one of the I bit related interrupt sources and
to elevate it to the highest I bit masked position of the priority resolution circuit. In addition, four
miscellaneous system control bits are included in this register.
RBOOT — Read Bootstrap ROM
SMOD and MDA — Special Mode Select and Mode Select A
IRVNE — Internal Read Visibility/Not E
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This bit can be read at any time. It can be written only in special modes (SMOD = 1). In special
bootstrap mode, it is set during reset. Reset clears it in all other modes.
These two bits can be read at any time.These bits reflect the status of the MODA and MODB input pins
at the rising edge of reset. SMOD may be written only in special modes. It cannot be written to a 1 after
being cleared without an interim reset. MDA may be written at any time in special modes, but only once
in normal modes. An interpretation of the values of these two bits is shown in
This bit may be read at any time. It may be written once in any mode. IRVNE is set during reset in
special test mode only, and cleared by reset in the other modes.
As shown in the table, in single-chip and bootstrap modes IRVNE determines whether the E clock is
driven out or forced low.
1 = Bootloader ROM is enabled in the memory map at $BF00–$BFFF.
0 = Bootloader ROM is disabled and is not in the memory map.
1 = Data from internal reads is driven out on the external data bus in expanded modes.
0 = Data from internal reads is not visible on the external data bus.
1 = E pin driven low
0 = E clock driven out of the chip
Address:
Reset:
Read:
Write:
MODB
RBOOT
1. The values of the RBOOT, SMOD, IRVNE, and MDA bits at reset depend on the
$003C
Bit 7
1
1
0
0
mode during initialization. Refer to
Inputs
Table 4-3. Hardware Mode Select Summary
Figure 4-7. Highest Priority I-Bit Interrupt
MODA
SMOD
and Miscellaneous Register (HPRIO)
6
0
1
0
1
Note 1
MC68HC711D3 Data Sheet, Rev. 2.1
MDA
5
Expanded multiplexed
Special bootstrap
Special test
Single chip
IRVNE
4
Mode
Table
PSEL3
4-3.
3
0
PSEL2
2
1
Latched at Reset
SMOD
0
0
1
1
PSEL1
1
0
MDA
Table
0
1
0
1
Freescale Semiconductor
PSEL0
Bit 0
1
4-3.