SAK-C167CS-L40M CA+ Infineon Technologies, SAK-C167CS-L40M CA+ Datasheet - Page 67

• Manufacturer Part Number: SAK-C167CS-L40M CA+
• Description: IC MCU 16BIT 40MHZ MQFP-144
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C167CS-L40M CA+

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144- BSQFP
• Data Bus Width: 16 bit
• Data Ram Size: 11 KB
• Interface Type: 1xUSART, 1xSSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 9
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Packages: PG-MQFP-144
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 11.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: K167CSL40MCAZNP; K167CSL40MCAZXP; SAK-C167CS-L40M CA+; SAK-C167CS-L40MCAIN; SAKC167CSL40MCAXT; SP000103490

AC Characteristics
Table 15
Parameter
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
1)
Figure 16
Variable Memory Cycles
The bus timing shown below is programmable via the BUSCONx registers. The duration
of ALE and two types of waitstates can be selected. This table summarizes the possible
bus cycle durations.
Table 16
Bus Cycle Type
Demultiplexed bus cycle
with normal ALE
Demultiplexed bus cycle
with extended ALE
Multiplexed bus cycle
with normal ALE
Multiplexed bus cycle
with extended ALE
Data Sheet
The CLKOUT cycle time is influenced by the PLL jitter (given values apply to
For a single CLKOUT cycle (2 TCL) the deviation caused by the PLL jitter is below 1 ns (for
For longer periods the relative deviation decreases (see PLL deviation formula).
CLKOUT
CLKOUT Reference Signal
CLKOUT Signal Timing
Variable Memory Cycles
tc
5
Bus Cycle Duration
4 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)
6 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)
6 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)
8 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)
tc
6
tc
63
7
Symbol
tc
tc
tc
tc
tc
5
6
7
8
9
Unit 25/33/40 MHz, 0 Waitstates
TCL 80 ns
TCL 120 ns / 90.9 ns / 75 ns
TCL 120 ns / 90.9 ns / 75 ns
TCL 160 ns / 121.2 ns / 100 ns
CC
CC 8
CC 6
CC –
CC –
tc
8
min.
f
CPU
40/30/25
/ 60.6 ns / 50 ns
tc
Limits
= 25/33/40 MHz).
9
max.
–
–
4
4
1)
C167CS-4R
f
V2.2, 2001-08
CPU
C167CS-L
> 25 MHz).
MCT04415
Unit
ns
ns
ns
ns
ns