SAK-C167CS-L40M CA+ Infineon Technologies, SAK-C167CS-L40M CA+ Datasheet - Page 61

• Manufacturer Part Number: SAK-C167CS-L40M CA+
• Description: IC MCU 16BIT 40MHZ MQFP-144
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C167CS-L40M CA+

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144- BSQFP
• Data Bus Width: 16 bit
• Data Ram Size: 11 KB
• Interface Type: 1xUSART, 1xSSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 9
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Packages: PG-MQFP-144
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 11.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: K167CSL40MCAZNP; K167CSL40MCAZXP; SAK-C167CS-L40M CA+; SAK-C167CS-L40MCAIN; SAKC167CSL40MCAXT; SP000103490

Due to this adaptation to the input clock the frequency of
it is locked to
duration of individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and
For a period of
deviation D
where
So for a period of 3 TCLs @ 25 MHz (i.e.
and (3TCL)
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see
Figure 12
Data Sheet
±26.5
(
±30
±20
±10
N
ns
±1
N
× TCL)
= number of consecutive TCLs and 1 ≤
Max. jitter
1
N
min
This approximated formula is valid for
1
:
N
Approximated Maximum Accumulated PLL Jitter
f
= 3TCL
min
OSC
5
40 and 10 MHz
N
D
=
N
. The slight variation causes a jitter of
× TCL the minimum value is computed using the corresponding
N
10
NOM
× TCL
- 1.288 ns = 58.7 ns (@
f
NOM
CPU
40 MHz.
- D
20
Figure
N
; D
N
N
57
[ns] = ± (13.3 +
= 3): D
12).
N
3
≤ 40.
f
CPU
= (13.3 +
= 25 MHz).
f
CPU
N
f
CPU
× 6.3) /
3
is constantly adjusted so
× 6.3) / 25 = 1.288 ns,
which also effects the
40
f
CPU
10 MHz
16 MHz
20 MHz
25 MHz
33 MHz
40 MHz
C167CS-4R
[MHz],
V2.2, 2001-08
C167CS-L
Figure
MCD04413B
N
12).