SAK-C167CS-L40M CA+ Infineon Technologies, SAK-C167CS-L40M CA+ Datasheet - Page 4

• Manufacturer Part Number: SAK-C167CS-L40M CA+
• Description: IC MCU 16BIT 40MHZ MQFP-144
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C167CS-L40M CA+

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144- BSQFP
• Data Bus Width: 16 bit
• Data Ram Size: 11 KB
• Interface Type: 1xUSART, 1xSSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 9
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Packages: PG-MQFP-144
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 11.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: K167CSL40MCAZNP; K167CSL40MCAZXP; SAK-C167CS-L40M CA+; SAK-C167CS-L40MCAIN; SAKC167CSL40MCAXT; SP000103490

C167CS
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Controller Area Network (CAN): License of Robert Bosch GmbH
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New package due to new assembly line. MQFP-144-1 for current deliveries only, will be discontinued.
27
Subjects (major changes from V2.1, 2000-12 to V2.2, 2001-08)
Figure 2
Figure 5
Output voltage/current specification improved
Limit values for
oscillator
Figure 10
Figure 12
Clock parameters adjusted
TUE note includes P1H
Package drawing updated
Subjects (major changes from V2.0, 2000-06 to V2.1, 2000-12)
Maximum operating frequency updated to 40 MHz
Derivative table updated
RSTIN level for
Current unit corrected to µ A
Input clock range adjusted
Note 5 detailed
Parameters
Relative bus timing parameters added
Parameter
Notes adapted
Parameter
Parameters
corrected (pins 98, 99)
and
corrected
updated for 40 MHz
tc
tc
tc
t
25
28
42
2001-08
2000-12
2000-06
1999-06
1999-03
Figure 6
10
,
changed, notes adapted
changed
I
I
,
t
IDO
DD
43
tc
,
12
corrected to
t
and
44
,
tc
,
updated
13
t
I
46
PDR
1)
,
,
tc
t
V2.1 (Intermediate version)
V2.0
(Advance Information)
47
14
increased due to the usage of a standard
,
changed
tc
V
IL
15
(was
,
tc
16
,
V
tc
IL2
17
)
,
tc
18
,
tc
19
changed
V2.2