SAK-C167CS-L40M CA+ Infineon Technologies, SAK-C167CS-L40M CA+ Datasheet - Page 59

• Manufacturer Part Number: SAK-C167CS-L40M CA+
• Description: IC MCU 16BIT 40MHZ MQFP-144
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C167CS-L40M CA+

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144- BSQFP
• Data Bus Width: 16 bit
• Data Ram Size: 11 KB
• Interface Type: 1xUSART, 1xSSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 9
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Packages: PG-MQFP-144
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 11.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: K167CSL40MCAZNP; K167CSL40MCAZXP; SAK-C167CS-L40M CA+; SAK-C167CS-L40MCAIN; SAKC167CSL40MCAXT; SP000103490

AC Characteristics
Definition of Internal Timing
The internal operation of the C167CS is controlled by the internal CPU clock
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see
Figure 11
The CPU clock signal
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
be regarded when calculating the timings for the C167CS.
Note: The example for PLL operation shown in
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
Data Sheet
Phase Locked Loop Operation
f
f
Direct Clock Drive
f
f
Prescaler Operation
f
f
OSC
CPU
OSC
CPU
OSC
CPU
Generation Mechanisms for the CPU Clock
f
CPU
can be generated from the oscillator clock signal
55
Figure 11
refers to a PLL factor of 4.
TCL
f
CPU
TCL
. This influence must
TCL
TCL
TCL
TCL
MCT04338
C167CS-4R
Figure
V2.2, 2001-08
C167CS-L
f
CPU
f
OSC
. Both
11).
via