UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 793

• Manufacturer Part Number: UPD70F3736GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3736GK-GAK-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 66
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

I
(T
Notes 1. At the start condition, the first clock pulse is generated after the hold time.
Remark n = 0, 1
2
SCL0n clock frequency
Bus free time
(Between start and stop conditions)
Hold time
SCL0n clock low-level width
SCL0n clock high-level width
Setup time for start/restart conditions
Data hold time
Data setup time
SDA0n and SCL0n signal rise time
SDA0n and SCL0n signal fall time
Stop condition setup time
Pulse width of spike suppressed by
input filter
Capacitance load of each bus line
C Bus Mode
A
= −40 to +85°C, V
2. The system requires a minimum of 300 ns hold time internally for the SDA0n signal (at V
3. If the system does not extend the SCL0n signal low hold time (t
4. The high-speed mode I
5. Cb: Total capacitance of one bus line (unit: pF)
Note 1
signal) in order to occupy the undefined area at the falling edge of SCL0n.
(t
high-speed mode I
• If the system does not extend the SCL0n signal’s low state hold time:
• If the system extends the SCL0n signal’s low state hold time:
HD
Parameter
t
Transmit the following data bit to the SDA0n line prior to the SCL0n line release (t
+ 250 = 1,250 ns: Normal mode I
:
DAT
SU
CBUS compatible
master
I
2
:
C mode
DAT
) needs to be satisfied.
≥ 250 ns
DD
= EV
CHAPTER 30
DD
2
C bus so that it meets the following conditions.
= AV
2
C bus can be used in the normal-mode I
f
t
t
t
t
t
t
t
t
t
t
t
Cb
REF0
CLK
BUF
HD:STA
LOW
HIGH
SU:STA
HD:DAT
SU:DAT
R
F
SU:STO
SP
Symbol
Preliminary User’s Manual U18952EJ1V0UD
= AV
<106>
<107>
<108>
<109>
<110>
<111>
<112>
<113>
<114>
<115>
<116>
ELECTRICAL SPECIFICATIONS (TARGET)
REF1
2
C bus specification).
= 2.2 to 3.6 V, V
MIN.
0
250
4.7
4.0
4.7
4.0
4.7
5.0
4.0
Note 2
0
−
−
−
−
Normal Mode
SS
= EV
MAX.
1000
100
300
400
−
−
−
−
−
−
−
−
−
−
SS
= AV
LOW
2
20 + 0.1Cb
20 + 0.1Cb
C bus system. In this case, set the
), only the maximum data hold time
SS
100
= 0 V)
MIN.
0
1.3
0.6
1.3
0.6
0.6
0.6
High-Speed Mode
Note 2
0
−
0
−
Note 4
Note 5
Note 5
Rmax.
0.9
MAX.
400
300
300
400
50
−
−
−
−
−
−
−
−
Note 3
+ t
IHmin.
SU:DAT
of SCL0n
= 1,000
Unit
kHz
μ
μ
μ
μ
μ
μ
μ
ns
ns
ns
μ
ns
pF
s
s
s
s
s
s
s
s
793