UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 308

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UPD70F3736GK-GAK-AX

Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3736GK-GAK-AX

Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
308
(f) TMQ0 capture/compare register 0 (TQ0CCR0)
(g) TMQ0 capture/compare registers 1 to 3 (TQ0CCR1 to TQ0CCR3)
If D
signal (INTTQ0CC0) is generated when the number of external event counts reaches (D
Usually, the TQ0CCR1 to TQ0CCR3 registers are not used in the external event count mode. However,
the set value of the TQ0CCR1 to TQ0CCR3 registers are transferred to the CCR1 to CCR3 buffer
registers. When the count value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer
registers, compare match interrupt request signals (INTTQ0CC1 to INTTQ0CC3) are generated.
Therefore, mask the interrupt signal by using the interrupt mask flags (TQ0CCMK1 to TQ0CCMK3).
Caution When an external clock is used as the count clock, the external clock can be input
Remark
0
Figure 8-11. Register Setting for Operation in External Event Count Mode (2/2)
is set to the TQ0CCR0 register, the counter is cleared and a compare match interrupt request
only from the TIQ00 pin. At this time, set the TQ0IOC1.TQ0IS1 and TQ0IOC1.TQ0IS0
bits to 00 (capture trigger input (TIQ00 pin): no edge detection).
used in the external event count mode.
The TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Preliminary User’s Manual U18952EJ1V0UD
0
+ 1).

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