UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 183

• Manufacturer Part Number: UPD70F3736GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3736GK-GAK-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 66
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.4
6.4.1
Note Lockup time
Remark
6.4.2
control register of port CM.
clock when it is in the operable status. It outputs a low level in the stopped status. However, the CLKOUT pin is in
the port mode (PCM1 pin: input mode) after reset and until it is set in the output mode. Therefore, the status of the pin
is Hi-Z.
Target Clock
Main clock oscillator (f
Subclock oscillator (f
CPU clock (f
Internal system clock (f
Main clock (in PLL mode, f
Peripheral clock (f
WT clock (main)
WT clock (sub)
WDT2 clock (internal oscillation)
WDT2 clock (main)
WDT2 clock (sub)
The following table shows the operation status of each clock.
The clock output function is used to output the internal system clock (f
The internal system clock (f
The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the
The status of the CLKOUT pin is the same as the internal system clock in Table 6-1 and the pin can output the
Operation
Operation of each clock
Clock output function
O
×:
:
CPU
Register Setting and
)
Operation Status
Operable
Stopped
XX
to f
XT
X
)
)
CLK
XX
/1,024)
)
XX
)
CLK
) is selected by using the PCC.CK3 to PCC.CK0 bits.
During
Reset
CHAPTER 6 CLOCK GENERATION FUNCTION
×
×
×
×
×
×
×
×
Table 6-1. Operation Status of Each Clock
Preliminary User’s Manual U18952EJ1V0UD
Stabilization
Time Count
Oscillation
During
CLK Bit = 0, MCK Bit = 0
×
×
×
×
Note
HALT
Mode
×
IDLE1,
IDLE2
Mode
×
×
×
×
×
PCC Register
STOP
Mode
CLK
×
×
×
×
×
×
×
) from the CLKOUT pin.
Subclock
Mode
CLS Bit = 1,
MCK Bit = 0
Sub-IDLE
Mode
×
×
×
×
Subclock
Mode
CLS Bit = 1,
MCK Bit = 1
×
×
×
×
×
Sub-IDLE
Mode
×
×
×
×
×
×
×
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