UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 453

• Manufacturer Part Number: UPD70F3736GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3736GK-GAK-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 66
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4) UARTAn option control register 0 (UAnOPT0)
Caution Do not set the UAnSRT and UAnSTT bits (to 1) during SBF reception (UAnSRF bit = 1).
The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTAn register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 14H.
(n = 0 to 2)
UAnOPT0
After reset: 14H
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
• SBF (Sync Brake Field) reception is judged during LIN communication.
• The UAnSRF bit is held at 1 when an SBF reception error occurs, and then SBF
• The UAnSRF bit is a read-only bit.
• This is the SBF reception trigger bit during LIN communication, and when read,
• Set the UAnSRT bit after setting the UAnPWR bit = UAnRXE bit = 1.
• This is the SBF transmission trigger bit during LIN communication, and when read,
• Set the UAnSTT bit after setting the UAnPWR bit = UAnTXE bit = 1.
UAnSRF
UAnSRT
UAnSTT
UAnSRF
reception is started again.
“0” is always read. For SBF reception, set the UAnSRT bit (to 1) to enable SBF
reception.
“0” is always read.
<7>
0
1
0
1
0
1
When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnRXE bit = 0 are set.
Also upon normal end of SBF reception.
During SBF reception
SBF reception trigger
SBF transmission trigger
UAnSRT UAnSTT UAnSLS2 UAnSLS1 UAnSLS0 UAnTDL UAnRDL
R/W
6
Preliminary User’s Manual U18952EJ1V0UD
Address: UA0OPT0 FFFFFA03H, UA1OPT0 FFFFFA13H,
5
UA2OPT0 FFFFFA23H
SBF transmission trigger
4
SBF reception trigger
SBF reception flag
−
−
3
2
1
0
(1/2)
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