UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 403
UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
UPD70F3736GK-GAK-AX
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Renesas Electronics America
Quantity:
10 000
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(2) Real-time output port control register 0 (RTPC0)
The RTPC0 register is a register that sets the operation mode and output trigger of the real-time output port.
The relationship between the operation mode and output trigger of the real-time output port is as shown in
Table 12-3.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
BYTE0
0
1
RTPC0
After reset: 00H
Notes 1. When the real-time output operation is disabled (RTPOE0 bit = 0), all the bits of the
Caution Set the RTPEG0, BYTE0, and EXTR0 bits only when RTPOE0 bit = 0.
Table 12-3. Operation Modes and Output Triggers of Real-Time Output Port
EXTR0
0
1
0
1
2. The INTTP0CC0 signal is output for 1 clock of the count clock selected by TMP0.
RTPOE0
RTPEG0
RTPOE0
BYTE0
< >
4 bits × 1 channel,
2 bits × 1 channel
6 bits × 1 channel
real-time output signals (RTP00 to RTP05) output “0”.
0
1
0
1
0
1
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)
Operation Mode
Disables operation
Enables operation
Falling edge
Rising edge
4 bits × 2 channels, 2 bits × 2 channels
6 bits × 2 channels
RTPEG0
R/W
Preliminary User’s Manual U18952EJ1V0UD
Specification of channel configuration for real-time output
Address: FFFFF6E5H
BYTE0
Note 2
Note 1
Control of real-time output operation
INTTP5CC0
Setting prohibited
Setting prohibited
INTTP0CC0
Valid edge of INTTP0CC0 signal
EXTR0
RTBH0 (RTP04, RTP05)
0
0
Setting prohibited
INTTP0CC0
RTBL0 (RTP00 to RTP03)
0
0
403
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