UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 421
UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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13.5 Operation
13.5.1 Basic operation
<1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the
<2> When A/D conversion is started, the voltage input to the selected analog input channel is sampled by the
<3> When the sample & hold circuit samples the input channel for a specific time, it enters the hold status, and
<4> Set bit 9 of the successive approximation register (SAR). The tap selector selects (1/2) AV
<5> The voltage difference between the voltage of the compare voltage generation DAC and the analog input
<6> Next, bit 8 of the SAR register is automatically set and the next comparison is started. Depending on the
<7> This comparison is continued to bit 0 of the SAR register.
<8> When comparison of the 10 bits is complete, the valid digital result is stored in the SAR register, which is then
<9> In one-shot select mode, conversion is stopped
ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set,
conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or
timer trigger mode.
sample & hold circuit.
holds the input analog voltage until A/D conversion is complete.
compare voltage generation DAC.
voltage is compared by the voltage comparator. If the analog input voltage is higher than (1/2) AV
MSB of the SAR register remains set. If it is lower than (1/2) AV
value of bit 9, to which a result has been already set, the voltage of the compare voltage generation DAC is
selected as follows.
• Bit 9 = 1: (3/4) AV
• Bit 9 = 0: (1/4) AV
This compare voltage and the analog input voltage are compared and, depending on the result, bit 8 is
manipulated as follows.
Analog input voltage ≥ Compare voltage: Bit 8 = 1
Analog input voltage ≤ Compare voltage: Bit 8 = 0
transferred to and stored in the ADA0CRn register. After that, an A/D conversion end interrupt request signal
(INTAD) is generated.
scanning once
cleared to 0. In continuous scan mode, repeat steps <2> to <8> for each channel.
Remark
Note In the external trigger mode, timer trigger mode 0, or timer trigger mode 1, the trigger standby status
is entered.
The trigger standby status means the status after the stabilization time has passed.
Note
. In continuous select mode, repeat steps <2> to <8> until the ADA0M0.ADA0CE bit is
REF0
REF0
Preliminary User’s Manual U18952EJ1V0UD
CHAPTER 13 A/D CONVERTER
Note
. In one-shot scan mode, conversion is stopped after
REF0
, the MSB is reset.
REF0
REF0
as the
, the
421
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