UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 424
UPD70F3736GK-GAK-AX
Manufacturer Part Number
UPD70F3736GK-GAK-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3736GK-GAK-AX.pdf
(830 pages)
Specifications of UPD70F3736GK-GAK-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
66
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
UPD70F3736GK-GAK-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(3) Timer trigger mode
In this mode, converting the signal of the analog input pin (ANI0 to ANI7) specified by the ADA0S register is
started by the compare match interrupt request signal (INTTP2CC0 or INTTP2CC1) of the capture/compare
register connected to the timer. The INTTP2CC0 or INTTP2CC1 signal is selected by the ADA0TMD1 and
ADA0TMD0 bits, and conversion is started at the rising edge of the specified compare match interrupt request
signal. When the ADA0CE bit is set to 1, the A/D converter waits for a trigger, and starts conversion when the
compare match interrupt request signal of the timer is input.
When conversion is completed, regardless of whether the continuous select, continuous scan, one-shot select,
or one-shot scan mode is set as the operation mode by the ADA0MD1 and ADA0MD0 bits, the result of the
conversion is stored in the ADA0CRn register. At the same time, the INTAD signal is generated, and the A/D
converter waits for the trigger again.
When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the
A/D converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is
stopped). If the valid trigger is input during the conversion operation, the conversion is aborted and started
again from the beginning.
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during conversion, the conversion
is stopped and the A/D converter waits for the trigger again. However, writing to these registers is prohibited in
the one-shot select mode/one-shot scan mode.
Caution To select the timer trigger mode, set the high-speed conversion mode. Do not input a trigger
Remark
during stabilization time that is inserted once after the A/D conversion operation is enabled
(ADA0M0.ADA0CE bit = 1).
The trigger standby status means the status after the stabilization time has passed.
Preliminary User’s Manual U18952EJ1V0UD
CHAPTER 13 A/D CONVERTER
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