D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 907

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.5.5
CANIMR is a 16-bit register that prevents all interrupts corresponding interrupts in the CANIRR
from generating on output signal on the IRQ. An interrupt request is masked if the corresponding
bit position is set to 1. This register can be read or written at any time. The CANIMR directly
controls the generation of IRQ, but does not prevent the setting of the corresponding bit in the
CANIRR.
Initial value:
Bit
0
R/W:
Bit:
Bit Name
IRR0
Interrupt Mask Register (CANIMR)
15
R
1
-
IMR14 IMR13 IMR12
R/W
14
1
R/W
13
1
Initial Value
1
R/W
12
1
11
R
1
-
R/W
R/W
10
R
1
-
IMR9 IMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR0
R/W
9
1
Description
Reset/Halt/Sleep Interrupt Flag
Indicates that the CAN Interface has been reset
or halted and the HCAN2 is now in Configuration
mode or HCAN2 is asleep. An interrupt signal will
be generated through this bit to notify the change
of the HCAN2's state to the host processor if a
MCR0 (Software reset) or MCR1 (Halt) or MCR5
(Sleep) request is made. The GSR may be read
after this bit is set to figure out which state
HCAN2 is in.
Important: When a Sleep mode request needs to
be made, the Halt mode should be used
beforehand. Refer to the MCR5 description.
0: Clearing condition: Write a 1 to this bit.
1: Transition to Software reset mode, Halt mode,
R/W
8
1
or Sleep mode.
Setting condition: When reset/halt processing
completed after Software reset (MCR0) or Halt
mode (MCR1) or Sleep mode (MCR5) is
requested.
R/W
7
1
Rev. 2.00 Feb. 12, 2010 Page 823 of 1330
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
REJ09B0554-0200
R/W
2
1
R/W
1
1
R/W
0
1