D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 678

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

17.3.9
SCFCR performs data count resetting and trigger data number setting for transmit and receive
FIFO registers, and also contains a loopback test enable bit.
SCFCR can always be read from and written to by the CPU.
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 594 of 1330
REJ09B0554-0200
Bit
15 to 11 —
10
9
8
7
6
R/W:
Bit:
FIFO Control Register (SCFCR)
Bit Name
RSTRG2*
RSTRG1*
RSTRG0*
RTRG1
RTRG0
15
R
0
-
14
-
R
0
1
1
1
13
R
0
-
Initial Value
All 0
0
0
0
0
0
12
R
0
-
11
R
0
-
RG2*
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
RST
10
0
1
RG1*
R/W
RST
9
0
1
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SCIF_RTS Output Active Trigger
The SCIF_RTS signal becomes high when the
number of receive data stored in SCFRDR
exceeds the trigger number shown below.
000:127
001:1
010:16
011:32
100:64
101:96
110:108
111:120
Receive FIFO Data Number Trigger
These bits are used to set the number of receive
data bytes that sets the RDF flag in SCFSR.
The RDF flag is set when the number of receive
data bytes in SCFRDR is equal to or greater than
the trigger set number shown below.
00:1
01:16
10:64
11:96
RG0*
R/W
RST
8
0
1
RTRG1
R/W
7
0
RTRG0
R/W
6
0
TTRG1
R/W
5
0
TTRG0
R/W
4
0
MCE*
R/W
3
0
1
TFRST
R/W
2
0
RFRST LOOP
R/W
1
0
R/W
0
0