D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 293

MPU 3V 8K,PB-FREE, 256-BGA

D17760BP200ADV

Manufacturer Part Number
D17760BP200ADV
Description
MPU 3V 8K,PB-FREE, 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of D17760BP200ADV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D17760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(10) Slot Illegal Instruction Exception
• Transition address: VBR + H'0000 0100
• Transition operations:
Slot_illegal_instruction_exception()
{
}
⎯ Decoding of an undefined instruction in a delay slot
⎯ Decoding of an instruction that modifies PC in a delay slot
⎯ Decoding in user mode of a privileged instruction in a delay slot
⎯ Decoding of a PC-relative MOV instruction or MOVA instruction in a delay slot
The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and
R15 contents when this exception occurred are saved in SSR and SGR.
Exception code H'1A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other
than H'FFFD is decoded.
Sources:
SPC = PC - 2;
SSR = SR;
SGR = R15;
EXPEVT = H'0000 01A0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0100;
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Undefined instruction: H'FFFD
Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm,SR, LDC.L @Rm+,SR
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC
instructions that access GBR
Rev. 2.00 Feb. 12, 2010 Page 209 of 1330
REJ09B0554-0200

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