D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 188

MPU 3V 8K,PB-FREE, 256-BGA

D17760BP200ADV

Manufacturer Part Number

D17760BP200ADV

Description

MPU 3V 8K,PB-FREE, 256-BGA

Manufacturer

Renesas Electronics America

Series

SuperH® SH7750r

Datasheet

1.D6417760BP200ADV.pdf (1418 pages)

Specifications of D17760BP200ADV

Core Processor

SH-4

Core Size

32-Bit

Speed

200MHz

Connectivity

Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB

Peripherals

DMA, LCD, POR, WDT

Number Of I /o

69

Program Memory Type

ROMless

Ram Size

48K x 8

Voltage - Supply (vcc/vdd)

1.4 V ~ 1.6 V

Data Converters

A/D 4x10b

Oscillator Type

Internal

Operating Temperature

-40°C ~ 85°C

Package / Case

256-BGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Eeprom Size

-

Program Memory Size

-

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

D17760BP200ADV

Manufacturer:

Renesas Electronics America

Quantity:

10 000

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Table 5.3

Rev. 2.00 Feb. 12, 2010 Page 104 of 1330

REJ09B0554-0200

Category

Data transfer

instructions

Functional

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

No.

1

2

Execution Cycles

Instruction

EXTS.B

EXTS.W

EXTU.B

EXTU.W

MOV

MOV

MOVA

MOV.W

MOV.L

MOV.B

MOV.W

MOV.L

MOV.B

MOV.W

MOV.L

MOV.B

MOV.W

MOV.L

MOV.B

MOV.W

MOV.L

MOV.B

MOV.W

MOV.L

MOV.B

MOV.W

MOV.L

MOV.B

MOV.W

MOV.L

MOV.B

MOV.W

MOV.L

Rm,Rn

Rm,Rn

Rm,Rn

#imm,Rn

@(disp,PC),R0

@(disp,PC),Rn

@(disp,PC),Rn

@Rm,Rn

@Rm,Rn

@Rm,Rn

@Rm+,Rn

@Rm+,Rn

@Rm+,Rn

@(disp,Rm),R0

@(disp,Rm),R0

@(disp,Rm),Rn

@(R0,Rm),Rn

@(R0,Rm),Rn

@(R0,Rm),Rn

@(disp,GBR),R0

@(disp,GBR),R0

@(disp,GBR),R0

Rm,@Rn

Rm,@Rn

Rm,@Rn

Rm,@-Rn

Rm,@-Rn

Rm,@-Rn

R0,@(disp,Rn)

R0,@(disp,Rn)

Rm,@(disp,Rn)

Rm,Rn

Rm,Rn

EX

EX

MT

EX

EX

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

LS

Instruc-

tion

Group

EX

EX

Issue

Rate

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

1

2

2

2

2

2

1/2

1/2

1/2

2

2

2

2

2

2

2

2

2

1

1

1

1/1

1/1

1/1

1

1

1

Latency

1

1

#1

#1

#1

#1

#1

#2

#2

#2

#2

#2

#2

#2

#2

#2

#2

#2

#2

#2

#2

#3

#3

#3

#2

#2

#2

#2

#2

#2

#2

#2

#2

Execution

Pattern

#1

#1

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Stage Start Cycles

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Lock

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

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