D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 715

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

18.3.1
SISMR is an 8-bit readable/writable register that selects settings for the communication format of
the smart card interface.
Bit
7, 6
5
4
3 to 0
Serial Mode Register (SISMR)
Bit
Name
⎯
PE
O/E
⎯
Initial
Value
All 0
1
0
All 0
Initial value:
R/W:
Bit:
R/W
R
R
R/W
R
7
0
R
-
Description
Reserved
These bits are always read as 0, and the write value
should always be 0.
Parity Enable
This bit is always read as 1.The write value should always
be 1.
Parity Mode
Selects whether even or odd parity is to be used when
adding a parity bit and checking parity.
0: Even parity*
1: Odd parity*
Notes: 1.
Reserved
These bits are always read as 0. The write value should
always be 0.
R
6
0
-
PE
R
5
1
2.
O/E
R/W
When even parity is specified, the
transmitter will add a parity bit if the
number of transmitted characters (1s) is
odd, so that the total number of set bits
(1s) is always even.
The receiver checks whether the total number
of set bits (1s), including a parity bit and
received characters, is even.
When odd parity is specified, the
transmitter will add a parity bit if the
number of transmitted characters (1s) is
even, so that the total number of set bits
(1s) is always odd.
The receiver checks whether the total number
of set bits (1s), including a parity bit and
received characters, is odd.
4
0
2
1
R
3
0
-
Rev. 2.00 Feb. 12, 2010 Page 631 of 1330
2
R
-
0
R
1
0
-
R
0
0
-
REJ09B0554-0200