D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 64

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 10.42 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface .............................. 358
Figure 10.43 Example of 32-Bit Data Width MPX Connection.................................................. 360
Figure 10.44 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait) ........ 360
Figure 10.45 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted) ... 361
Figure 10.46 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No External Wait) ....... 362
Figure 10.47 MPX Interface Timing 4 (Single Write, AnW = 1,
Figure 10.48 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait,
Figure 10.49 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control,
Figure 10.50 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait,
Figure 10.51 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control,
Figure 10.52 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait,
Figure 10.53 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait
Figure 10.54 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait,
Figure 10.55 MPX Interface Timing 12 (Burst Write Cycle, AnW = 1, One External Wait
Figure 10.56 Example of 32-Bit Data Width Byte Control SRAM............................................. 370
Figure 10.57 Byte Control SRAM Basic Read Cycle (No Wait) ................................................ 371
Figure 10.58 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) ....................... 372
Figure 10.59 Byte Control SRAM Basic Read Cycle
Figure 10.60 Wait Cycles between Access Cycles...................................................................... 375
Figure 10.61 Arbitration Sequence.............................................................................................. 377
Section 11 Direct Memory Access Controller (DMAC)
Figure 11.1 DMAC Block Diagram .......................................................................................... 380
Figure 11.2 DMABRG Block Diagram..................................................................................... 381
Figure 11.3 DMAC Transfer Flowchart .................................................................................... 425
Figure 11.4 Round Robin Mode ................................................................................................ 429
Figure 11.5 Example of Changes in Priority Order in Round Robin Mode............................... 431
Figure 11.6 Data Flow in Single Address Mode........................................................................ 432
Figure 11.7 DMA Transfer Timing in Single Address Mode.................................................... 433
Figure 11.8 Operation in Dual Address Mode........................................................................... 434
Figure 11.9 Example of Transfer Timing in Dual Address Mode ............................................. 435
Figure 11.10 Example of DMA Transfer in Cycle Steal Mode ................................................... 436
Rev. 2.00 Feb. 12, 2010 Page lxii of lxxxii
REJ09B0554-0200
One External Wait Inserted)................................................................................... 363
32-Bit Bus Width, 32-Byte Data Transfer) ............................................................ 364
32-Bit Bus Width, 32-Byte Data Transfer) ............................................................ 364
32-Bit Bus Width, 32-Byte Data Transfer) ............................................................ 365
32-Bit Bus Width, 32-Byte Data Transfer) ............................................................ 365
32-Bit Bus Width, 64-Bit Data Transfer) ............................................................... 366
Inserted, 32-Bit Bus Width, 64-Bit Data Transfer) ................................................ 367
32-Bit Bus Width, 64-Bit Data Transfer) ............................................................... 368
Inserted, 32-Bit Bus Width, 64-Bit Data Transfer) ............................................... 369
(One Internal Wait + One External Wait) .............................................................. 373