D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 524

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.4.5
(1) Number of Bus Cycles
The number of bus cycles when the DMAC is the bus master is controlled by the bus state
controller (BSC) just as it is when the CPU is the bus master. See section 10, Bus State Controller
(BSC), for details.
(2) DREQ Pin Sampling Timing
In external request mode, the DMAC samples the DREQ pin at the rising edge of a CKIO clock
signal. When detecting a DREQ input, the DMAC generates a bus cycle and performs DMA
transfer after four CKIO cycles at the earliest.
In the case of DREQ falling edge sampling, the DMAC detects a DREQ input after two CKIO
cycles (in the case of low-level sampling, one CKIO cycle).
The second and subsequent DREQ sampling operations are performed one cycle after the start of
the first DMAC transfer bus cycle (in the case of external request 2-channel mode and single
address mode).
DRAK is output for one cycle only, once each time DREQ is detected, regardless of the transfer
mode or DREQ detection method. In the case of burst mode edge detection, DREQ is sampled in
the first cycle only, and so DRAK is output in the first cycle only.
Rev. 2.00 Feb. 12, 2010 Page 440 of 1330
REJ09B0554-0200
CPU
CPU
Number of Bus Cycles and DREQ Pin Sampling Timing
Priority order:
Channel 0:
Channel 1:
Figure 11.12 Bus Handling with Two DMAC Channels Operating
DMAC CH1
DMAC channel 1
burst mode
DMAC CH1
Round robin mode
Cycle steal mode
Burst mode (edge-sensing)
DMAC CH0
CH0
DMAC channel 0 and
channel 1 round robin
mode
DMAC CH1
CH1
DMAC CH0
CH0
DMAC CH1
DMAC channel 1
burst mode
DMAC CH1
CPU
CPU