D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 426

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(11) Changing the Burst Length
When synchronous DRAM is connected to this LSI with a 32-bit memory bus width, a burst
length of either 4 or 8 is specifiable with the SDBL bit in BCR3. For more details, see the
description of the BCR3 register.
(a) Burst Read
Rev. 2.00 Feb. 12, 2010 Page 342 of 1330
REJ09B0554-0200
Figure 10.31 is the timing chart for burst-read operations. In the example shown below, two
synchronous DRAMs of 512k × 16 bits × 2 banks are assumed to be connected and used with a
32-bit data width and a burst length of 8. After the Tr cycle which outputs an ACTV
command, a READA command is issued in cycle Tc1. During cycles Td1 to Td8, the read data
are fetched at the rising edges of the off-chip command clock (CKIO). Tpc is the cycle used to
wait for completion of auto-precharging, which is triggered by the READA command, in the
synchronous DRAM. During this cycle, no new command that accesses the same bank can be
issued. In this LSI, bits TPC2 to TPC0 in MCR are used to determine the number of Tpc
cycles, and no commands are issued for the synchronous DRAM during these cycles.
Figure 10.30 (2) Synchronous DRAM Mode Write Timing (Mode Register Setting)
Precharge-sel
Address
D31−D0
RD/WR
CASS
CKIO
Bank
RAS
CKE
CSn
TRp1
(High)
TRp2
TRp3
TRp4
TMw1
TMw2
TMw3
TMw4
TMw5