HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 937
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
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The serial bit clock frequency can be computed using the following formula:
When the HSPI is configured as a slave, the IDIV and CLKC bits are ignored and the HSPI
synchronizes to the externally supplied serial bit clock. The maximum value of the external serial
bit clock that the module can operate with is peripheral clock frequency / 8.
If any of the FBS, CLKP, IDIV or CLKC bit values are changed, then the HSPI will undergo the
HSPI software reset.
Bit
5
4 to 0
Serial bit clock frequency =
Bit Name
IDIV
CLKC
4 to 0
Initial Value
0
All 0
(Initial clock division × (Clock division count + 1) × 2
R/W
R/W
R/W
Description
Initial Clock Division Ratio
0: The peripheral clock is divided by a factor of 4
1: The peripheral clock is divided by a factor of 32
Clock Division Count
These bits determine the number of intermediate
frequency cycles long both the high and low
periods of the serial bit clock.
00000: 1 intermediate frequency cycle.
00001: 2 Intermediate frequency cycles.
00010: 3 intermediate frequency cycles.
11111: 32 intermediate frequency cycles.
initially to create an intermediate frequency,
which is further divided to create the serial bit
clock when master mode.
initially to create an intermediate frequency,
which is further divided to create the serial bit
clock when master mode.
:
Serial bit clock frequency = Intermediate
frequency / 2.
Serial bit clock frequency = Intermediate
frequency / 4.
Serial bit clock frequency = Intermediate
frequency / 6.
Serial bit clock frequency = Intermediate
frequency / 64.
Pck
Rev. 2.00 Feb. 12, 2010 Page 853 of 1330
REJ09B0554-0200
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