HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 156
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
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Note: For the addressing modes below that use a displacement (disp), the assembler descriptions
Rev. 2.00 Feb. 12, 2010 Page 72 of 1330
REJ09B0554-0200
Addressing
Mode
PC-relative
Immediate
in this manual show the value before scaling (×1, ×2, or ×4) is performed according to the
operand size. This is done to clarify the operation of the LSI. Refer to the relevant
assembler notation rules for the actual assembler descriptions.
@ (disp:4, Rn)
@ (disp:8, GBR) ; GBR indirect with displacement
@ (disp:8, PC)
disp:8, disp:12
Instruction
Format
disp:12
Rn
#imm:8
#imm:8
#imm:8
; Register indirect with displacement
; PC-relative with displacement
; PC-relative
Effective Address Calculation Method
Effective address is PC + 4 with 12-bit
displacement disp added after being sign-extended
and
multiplied by 2.
Effective address is sum of PC + 4 and Rn.
8-bit immediate data imm of TST, AND, OR, or
XOR instruction is zero-extended.
8-bit immediate data imm of MOV, ADD, or
CMP/EQ instruction is sign-extended.
8-bit immediate data imm of TRAPA instruction is
zero-extended and multiplied by 4.
(sign-extended)
disp
PC
PC
Rn
4
2
4
+
×
+
+
+
PC + 4 + disp × 2
PC + 4 + Rn
Calculation
Formula
PC + 4 + disp
× 2 → Branch-
Target
PC + 4 + Rn
→ Branch-
Target
—
—
—
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