HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 249
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
- Current page: 249 of 1418
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Examples
Example 1 A store instruction accessing internal RAM occurs within four instructions after an
MOV.L #H'0C400000, R0
MOV.L #H'7C000204, R1
MOV.L @R0, R2
NOP
NOP
NOP
MOV.L R3, @R1
Example 2 A store instruction accessing internal RAM occurs within four instructions after an
MOV.L #H'7C002000, R1
MOV.L #H'12345678, R0
NOP
NOP
NOP
MOV.L R0, @R1
Example 3 A debugging tool generates a break to swap an instruction.
Original Instruction String After Instruction Swap Break
MOV.L #H'C000000, R0
ADD R0, R0
MOV.L R1, @R0
instruction generating a TLB miss exception.
instruction causing an interrupt to be accepted.
MOV.L #H'7C000000, R0
MOV.L R1, @R0
TRAPA #H'01
R0 is an address causing a TLB miss.
R1 is an address mapped to internal RAM.
TLB miss exception occurs.
1st word
2nd word
3rd word
Store instruction accessing internal RAM
R1 is an address mapped to internal RAM.
An interrupt is accepted after this instruction.
1st word
2nd word
3rd word
Store instruction accessing internal RAM
Contains address corresponding to R0.
R0 address is not a problem in original
instruction string.
Internal RAM is accessed by a store
operation because ADD is not executed.
The store is cancelled, but 2LW starting
at H'7C002000 is corrupted.
Rev. 2.00 Feb. 12, 2010 Page 165 of 1330
REJ09B0554-0200
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