HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1152
HD6417760BL200AV
Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BL200AV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Company:
Part Number:
HD6417760BL200AV
Manufacturer:
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Quantity:
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Part Number:
HD6417760BL200AV
Manufacturer:
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Quantity:
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30.3.1
This LCDC can select bus clock, the peripheral clock, or the external clock as its operation clock
source. It is also possible to include a divider of 1/1 to 1/16 in the selected clock and use the
division as the LCDC operating clock (DOTCLK). The clock output from the LCDC is used to
generate the synchronous clock output (LCD_CL2) for the LCD panel from the operating clock
selected in this register. The frequency of the output clock is LCD_CL2 = DOTCLK for a TFT
panel, and LCD_CL2 = (DOTCLK/width of data bus output to LCD panel) for an STN or DSTN
panel. The LDICKR must be set so that the clock input to the LCDC is 50 MHz or less regardless
of the LCD_CL2.
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 1068 of 1330
REJ09B0554-0200
Bit
15, 14
13
12
11 to 9
8
7 to 5
4
3
2
1
0
R/W:
Bit:
LCDC Input Clock Register (LDICKR)
Bit Name
⎯
ICKSEL1
ICKSEL0
⎯
⎯
⎯
DCDR4
DCDR3
DCDR2
DCDR1
DCDR0
15
R
0
-
14
R
0
-
SEL1
R/W
ICK
13
0
Initial Value
All 0
0
0
All 0
1
All 0
0
0
0
0
1
SEL0
R/W
ICK
12
0
11
R
0
-
10
R
0
-
R/W
R
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R
9
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Input Clock Select
Set the clock source for DOTCLK.
00: Bus clock is selected (Bck)
01: Peripheral clock is selected (Pck)
10: External clock is selected (LCD_CLK)
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
This bit is always read as 1. The write value
should always be 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Division Ratio
Set the input clock division ratio. For details on the
setting, refer to table 30.3.
R
8
-
1
7
0
R
-
0
R
6
-
R
5
0
-
DCDR4
R/W
4
0
DCDR3 DCDR2DCDR1DCDR0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
1
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